zl50052 Zarlink Semiconductor, zl50052 Datasheet
zl50052
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zl50052 Summary of contents
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... Timing Unit C8i PLL V DD_PLL Figure 1 - ZL50052 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs ZL50052GAC • ...
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... V core supply voltage • 3.3 V I/O supply voltage • tolerant inputs, outputs and I/Os Applications • Central Office Switches (Class 5) • Media Gateways • Class-Independent Switches • Access Concentrators • Scalable TDM-Based Architectures • Digital Loop Carriers ZL50052 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Device Overview The ZL50052 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports operate at 32.768 Mbps. The ZL50052 contains two data memory blocks (Backplane and Local) to provide the following switching path configurations: • Input-to-Output Unidirectional, supporting switching • ...
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... Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ZL50052 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Advancement Registers (LOAR0 to LOAR7 13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0 13.6 Backplane Output Advancement Registers (BOAR0 - BOAR7 13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0 13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.8 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ZL50052 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50052 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50052 PBGA Connections (196 PBGA mm) Pin Diagram (as viewed through top of package Figure 3 - 8,192 x 8,192 Channels (32 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - 4,096 x 4,096 Channels (32 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5 - 6,144 x 2,048 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram Figure 7 - Input and Output (Generated) Frame Pulse Alignment ...
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... Table 18 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 19 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 20 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 21 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 22 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ZL50052 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... OPEN L IC_ IC_ IC_ OPEN OPEN OPEN M IC_ IC_ D15 OPEN OPEN N IC_ D13 D10 OPEN P GND D9 D8 Figure 2 - ZL50052 PBGA Connections (196 PBGA mm) Pin Diagram ZL50052 A12 A13 R A11 A14 ODE ...
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... N10 FP8o N11 C16o M9 ZL50052 Description Master Clock (5 V Tolerant Schmitt-Triggered Input) This pin accepts an 8.192 MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register. Input data on both the Backplane and Local sides (BSTi0-7 and LSTi0-7) must be aligned to this clock and the accompanying input frame pulse, FP8i ...
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... BORS G2 BSTo0-7 B3, A1, A2, C4, C5, B2, D2, C2 ZL50052 Description Frame Pulse Output (5 V Tolerant Three-state Output) When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin outputs a 61 ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs a 122 ns-wide frame pulse. The frame pulse, running at 8 kHz rate, will have the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i) ...
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... DS C8 R/W A9 DTA D9 ZL50052 Description Local Output Reset State (5 V Tolerant Input with Internal Pull-down) When this input is LOW, the device will initialize with the LSTo0-7 outputs driven high. Following initialization, the Local stream outputs are always active. When this input is HIGH, the device will initialize with the LSTo0-7 outputs at high impedance ...
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... H12, J5, J10, K6, K7, K8 DD_PLL ZL50052 Description Device Reset (5 V Tolerant Input with Internal Pull-up) This input (active LOW) asynchronously applies reset and synchronously releases reset to the device. In the reset state, the outputs LSTo0-7 and BSTo0-7 are set to a HIGH or high impedance state, depending on the state of the LORS and BORS external control pins, respectively ...
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... Unidirectional and Bi-directional Switching Applications The ZL50052 has a maximum capacity of 8,192 input channels and 8,192 output channels. This is calculated from the number of streams and channels: 16 input streams (8 Backplane, 8 Local) at 32.768 Mbps and 16 output streams (8 Backplane, 8 Local) at 32.768 Mbps, with each stream providing 512 channels. ...
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... Backplane input to Local output switching. 1.1 Flexible Configuration The ZL50052 can be configured non-blocking unidirectional digital switch non-blocking bi-directional digital switch blocking switch with various switching capacities. 1.1.1 ...
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... Blocking Bi-directional Configuration The ZL50052 can be configured as a blocking bi-directional switch application requirement. For example, it can be configured bi-directional blocking switch, as shown in Figure 5: • 6,144 channel x 2,048 channel blocking switching from Backplane input to Local output streams • ...
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... The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 6, “ST-BUS and GCI-Bus Input Timing Diagram”. The ZL50052 device will automatically detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame pulse ...
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... Input Frame Pulse and Generated Frame Pulse Alignment The ZL50052 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during Frame N is output during Frame N+2 ...
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... MHz frequency. Therefore, jitter tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the carrier frequency. In the case of the ZL50052, the input clock is 8.192 MHz, and the jitter associated with this clock can have the highest frequency component at 4.096 MHz. ...
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... BSTi/LSTi0-7 Bit Delay = 1 Ch510 BSTi/LSTi0-7 2 Bit Delay = 7 1/2 Ch510 BSTi/LSTi0-7 Bit Delay = 7 3/4 Please refer to Control Register (Section 13.1) for SMPL_MODE definition. Figure 8 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 32 Mbps ZL50052 Ch511 Ch0 Bit Delay, 1/4 ...
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... The Local and Backplane Output Advancement Registers, LOAR0 - LOAR7 and BOAR0 - BOAR7, are used to control the Local and Backplane output advancement respectively. The advancement is determined with reference to the internal system clock rate (131.072 MHz). The advancement can cycle, -2 cycles or -3 cycles, which converts to approximately 0 ns, -7.6 ns shown in Figure 10. ZL50052 Ch511 Ch0 0 ...
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... The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE. RESET ODE (input pin) (input pin Table 1 - Local and Backplane Output Enable Control Priority ZL50052 Bit Advancement, 0 Ch511 Bit 0 Bit 7 Bit Advancement, -1 Ch511 Bit 0 Bit 7 Bit Advancement, -2 Ch511 Bit 0 Bit 7 Bit Advancement, -3 Bit 0 Bit 7 ...
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... Frame Frame N Serial Input Data Frame N Data Serial Output Data Frame N-2 Data Figure 11 - Data Throughput Delay with Input Ch0 Switched to Output Ch0 ZL50052 LE/BE OSB (Local / LORS/BORS (Control Backplane (input pin) Register bit) ...
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... Power-Up Sequence The recommended power-up sequence is for the V power-up of the V and V DD_PLL DD_CORE powered-up simultaneously, but neither should 'lead' the V All supplies may be powered-down simultaneously. ZL50052 Frame N+1 Frame N+2 Frame N+3 Frame N+1Data Frame N+2 Data Frame N+3 Data 2 Frames + ( Frame N-1 Data Frame N Data ...
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... Figure 14. This can be achieved, for example, by synchronizing the de-assertion of the reset signal with the input frame pulse FP8i. FP8i RESET (case 1) RESET (case RESET assertion De-assertion of RESET must not fall within this window ZL50052 RESET de-assertion Figure 14 - Hardware RESET De-assertion 24 Zarlink Semiconductor Inc. Data Sheet ...
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... When the Memory Block Programming mode is enabled, the contents of the Block Programming Register (BPR) will be loaded into the connection memories. See Table 11 and Table 12 for details of the Control Register and Block Programming Register values, respectively. ZL50052 Source Stream No. Source Channel No. ...
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... Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The memory test result is monitored through the Memory BIST Register. 10.0 JTAG Port The ZL50052 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. ZL50052 12 ...
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... TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when not driven from an external source. This pin MUST be pulled low for normal operation. 10.2 TAP Registers The ZL50052 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an Instruction Register and three Test Data Registers. 10.2.1 Test Instruction Register The JTAG interface contains a 4-bit instruction register ...
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... The Device Identification Register The JTAG device ID for the ZL50052 is 0C38414B Version, Bits <31:28>: 0000 Part No., Bits <27:12>: 1100 0011 1000 0100 Manufacturer ID, Bits <11:1>: 0001 0100 101 Header, Bit <0> (LSB): 1 10.3 Boundary Scan Description Language (BSDL) File A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149 ...
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... Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-7) in place of data defined by the Source Control, Stream and Channel Address bits. ZL50052 Description Table 6 - Local Data Memory (LDM) Bits ...
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... Backplane Message Mode Bit When LOW, the channel is in Connection Mode (data to be output on channel originated in Backplane or Local Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Backplane Connection Memory). ZL50052 Description Description 30 Zarlink Semiconductor Inc. ...
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... Local Output Advancement Register LOAR0 - 00A3 - 00AA Backplane Output Advancement Register BOAR0 - 014D Memory BIST Register, MBISTR H 3FFF Device Identification Register, DIR H Table 10 - Address Map for Registers (A14 = 0) ZL50052 Description Register 31 Zarlink Semiconductor Inc. Data Sheet ...
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... Output Clock Polarity When LOW, the output clock has the same polarity as the input clock. When HIGH, the output clock is inverted. This applies to both the 8 MHz (C8o) and 16 MHz (C16o) output clocks. ZL50052 Description , the Frame Boundary Discriminator can handle both low B ...
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... Local Connection Memory (LCM) for read or write operations. 01 selects Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 11 - Control Register Bits (continued) ZL50052 Description ODE Pin OSB bit BSTo0-7, LSTo0-7 ...
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... ZL50052 (a) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (c) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL ...
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... FP8i (g) Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (h) Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 16 - Frame Boundary Conditions, GCI-Bus Operation Zarlink Semiconductor Inc. ZL50052 Frame Boundary 35 Data Sheet ...
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... BPE 0 Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 s, upon completion of programming. Set LOW to abort the programming operation. Table 12 - Block Programming Register Bits ZL50052 Description 36 Zarlink Semiconductor Inc. Data Sheet . ...
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... This means that bits can be delayed by an integer value and that the sampling point can vary from 1/4 to 4/4 in 1/4 bit increments. Table 14 illustrates the bit delay and sampling point selection. ZL50052 Reset Description ...
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... Table 14 - Local Input Bit Delay and Sampling Point Programming Table ZL50052 SMPL_MODE = LOW Input Data Input Data LID0 Bit Delay Bit Delay 0 0 (Default) 0 (Default 1/4 ...
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... When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2] refers to the integer bit delay value ( bits). This means that bits can be delayed by an integer value and that the sampling point can vary from 1/4 to 4/4 in 1/4 bit increments. ZL50052 Reset Description ...
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... Table 16 - Backplane Input Bit Delay and Sampling Point Programming Table ZL50052 SMPL_MODE = LOW Input Data BID1 BID0 Bit Delay (Default 1/2 ...
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... When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Local Output Advancement Clock Rate 131.072 MHz Table 18 - Local Output Advancement (LOAR) Programming Table ZL50052 Reset Name Value Reserved ...
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... When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Backplane Output Advancement Clock Rate 131.072 MHz Table 20 - Backplane Output Advancement (BOAR) Programming Table ZL50052 Reset Name Value Reserved ...
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... Backplane Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Backplane Connection Memory BIST sequence (indicated by assertion of BISTCCB). A HIGH indicates Pass, a LOW indicates Fail. Table 21 - Memory BIST Register (MBISTR) Bits ZL50052 Description 43 Zarlink Semiconductor Inc. Data Sheet ...
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... The DIR register is configured as follows: Bit Name Reset Value 15:8 Reserved 7:4 RC[3:0] 3 Reserved 2:0 DID[2:0] Table 22 - Device Identification Register (DIR) Bits ZL50052 Description 0 Reserved Will be set normal operation 0000 Revision Control Bits 0 Reserved Will be set normal operation 101 Device ID 44 Zarlink Semiconductor Inc ...
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... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Operating Temperature 2 Positive Supply 3 Positive Supply 4 Positive Supply 5 Input Voltage 6 Input Voltage Tolerant Inputs Voltages are with respect to ground (V ) unless otherwise stated. SS ZL50052 Symbol Min. V -0.5 DD_CORE V -0.5 DD_IO V -0.5 DD_PLL V -0 -0.5 I_5V ...
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... Output Low Voltage High-Impedance Leakage Output Pin Capacitance S Voltages are with respect to ground (V ) unless otherwise stated. ss Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V). ZL50052 Sym. Min. Typ. Max DD_Core I 240 290 DD_Core I 100 ...
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... FP8o Output Delay (from output frame boundary to frame pulse edge) 13 C8o Clock Period 14 C8o Clock Pulse Width High 15 C8o Clock Pulse Width Low 16 C8o Clock Rise/Fall Time ZL50052 Sym. Level Units V 0 3.0 V < DD_IO V 0 3.0 V < V ...
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... FP16o Output Delay (from output frame boundary to frame pulse edge) 20 C16o Clock Period 21 C16o Clock Pulse Width High 22 C16o Clock Pulse Width Low 23 C16o Clock Rise/Fall Time ZL50052 Sym. Min. Typ. t 117 122 OFPW16_122 OFPW16_61 t 58 ...
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... Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 17 - Input and Output Clock Timing Diagram for ST-BUS ZL50052 t IFPW244 t ...
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... Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 18 - Input and Output Clock Timing Diagram for GCI-Bus ZL50052 t IFPW244 t ...
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... CK_int * L/BSTi0 32.768 Mbps FP8o C8o CK_int * L/BSTo0-7 Bit1 Bit1 32.768 Mbps Ch511 Ch511 Note *: CK_int is the internal clock signal of 131.072 MHz. Figure 19 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps) ZL50052 Sym. Min. Typ IDS32 t 2 SIS32 t 2 SIH32 t 7 OFBOS ...
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... C8i CK_int * L/BSTi0 32.768 Mbps FP8o C8o CK_int * L/BSTo0-7 Bit5 Bit6 32.768 Mbps Ch511 Ch511 Note *: CK_int is the internal clock signal of 131.072 MHz. Figure 20 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps) ZL50052 t IDS32 t SIS32 t SIH32 OFBOS t SOD32 Bit0 Bit1 ...
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... Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Note 1: High Impedance is measured by pulling to the appropriate rail with CLK STo STo Figure 21 - Serial Output and External Control ODE ZL50052 Sym. Min. Typ. Max ...
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... MHz 13 2 MHz 14 4 MHz ZL50052 32.768 Mbps Data Rate Units Jitter Tolerance 600 ns 600 ...
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... Note 2: There must be a minimum between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a minimum must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access). ZL50052 Sym. Min. Typ. Max CSS ...
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... DS CS R/W A0-A14 D0-D15 READ D0-D15 WRITE DTA Figure 23 - Motorola Non-Multiplexed Bus Timing ZL50052 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t RDS t AKD 56 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH RDH V TT ...
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... TDi Input Set-up Time 7 TDi Input Hold Time 8 TDo Output Delay 9 TRST pulse width † Characteristics are over recommended operating conditions unless otherwise stated. TCK t TMSS TMS t TDIS TDi TDo TRST ZL50052 Sym. Min. t 100 TCKP t 80 TCKH t 80 TCKL t 10 TMSS t 10 ...
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... TOP VIEW NOTES:- 1. Controlling dimensions are in MM. 2. Seating plane is defined by the spherical crown of the solder balls. 3. Not to scale. 4. Ball arrangement array c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD BOTTOM VIEW SIDE VIEW Previous package codes: DIMENSION ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...