zl50052 Zarlink Semiconductor, zl50052 Datasheet - Page 26

• Manufacturer Part Number: zl50052
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 32 Mbps , And 16 Inputs And 16 Outputs
• Manufacturer: Zarlink Semiconductor

8.3.1
•
•
The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into
bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as
shown in Table 4.
The Block Programming Register bit, BPE will be automatically reset LOW within 125 s, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the
Block Programming Register or the MBP bit of the Control Register.
Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a
device reset, can be used.
During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS
pins, irrespective of the values in bits[14:13] of the connection memory.
9.0
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 13.7, Memory BIST Register).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register.
10.0
The ZL50052 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit
shall be controlled by an external Test Access Port (TAP) Controller.
BBPD2
LBPD2
Set the MBP bit in the Control Register from LOW to HIGH.
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection
Memory. The remaining bit positions are loaded with zeros as shown in Table 3.
15
15
Memory Built-In-Self-Test (BIST) Mode
Memory Block Programming Procedure
JTAG Port
BBPD1
LBPD1
14
14
Table 4 - Backplane Connection Memory in Block Programming Mode
Table 3 - Local Connection Memory in Block Programming Mode
LBPD0
BBPD0
13
13
12
0
12
0
11
0
11
0
Zarlink Semiconductor Inc.
10
0
10
ZL50052
0
9
0
26
9
0
8
0
8
0
7
0
7
0
6
0
6
0
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
Data Sheet
1
0
1
0
0
0
0
0