zl50052 Zarlink Semiconductor, zl50052 Datasheet - Page 17

• Manufacturer Part Number: zl50052
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 32 Mbps , And 16 Inputs And 16 Outputs
• Manufacturer: Zarlink Semiconductor

For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS
frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated
otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to
the output ports. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master
frame pulse (FP8i). The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register
bit, COPOL. An analog phase lock loop (APLL) is used to multiply the input clock frequency on C8i to generate an
internal clock signal operating at 131.072 MHz.
2.3
The ZL50052 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are
aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to
the output of the device such that data which is input during Frame N is output during Frame N+2.
For further details of frame pulse conditions and options, see Section 13.1, Control Register (CR), Figure 15,
“Frame Boundary Conditions, ST-BUS Operation”, and Figure 16, “Frame Boundary Conditions, GCI-Bus
Operation”.
Figure 7 illustrates the input and output frame pulse alignment. The t
pulse, FP8i, and the generated output frame pulse, FP8o. Refer to the “AC Electrical Characteristics”, on page 47.
Note that although this figure shows the traditional setups of the frame pulses and clocks for both ST-BUS and
(32 Mbps) GCI-Bus
(32 Mbps) ST-BUS
FP8i (GCI-Bus)
FP8i (ST-BUS)
Input Frame Pulse and Generated Frame Pulse Alignment
C8i (GCI-Bus)
BSTi/LSTi0-7
BSTi/LSTi0-7
C8i (ST-BUS)
(8.192 MHz)
(8.192 MHz)
BSTo/LSTo0-7
BSTi/LSTi0-7
(8 kHz)
(8 kHz)
(32 Mbps)
(32 Mbps)
FP8o
FP8i
C8o
C8i
3
4
2
5
Figure 7 - Input and Output (Generated) Frame Pulse Alignment
1 0
6 7
CH
7
0
0
Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram
CH
0
1
6
1
1
2
5
2
Channel 0
Channel 0
2
3
t
FBOS
3
4
3
4
4
3
4
5
5
6
2
5
6
7
Channel 0
1 0
6 7
7
8
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
7
0
Zarlink Semiconductor Inc.
6
1
Channel 1
5
Channel 1
2
ZL50052
4
3
3
4
2
5
17
1 0
6 7
FBOS
6
1
5
2
Channel 510
Channel 510
4
3
is the offset between the input frame
3
4
2
5
Channel 255
1 0
6 7
7
0
6
1
Channel 511
5
Channel 511
2
4
3
3
4
2
5
1 0
6 7
Data Sheet
7 6
0 1