zl50052 Zarlink Semiconductor, zl50052 Datasheet - Page 39

• Manufacturer Part Number: zl50052
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 32 Mbps , And 16 Inputs And 16 Outputs
• Manufacturer: Zarlink Semiconductor

13.4
Addresses 0063
There are 8 Backplane Input Delay Registers (BIDR0 to BIDR7).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and BIDR0 to BIDR7 define the input bit and fractional bit delay of each Backplane stream. The possible bit
delay adjustment is up to 7 3/4 bits, in steps of 1/4 bit.
When the SMPL_MODE bit is HIGH, BIDR0 to BIDR7 define the input bit sampling point as well as the integer bit
delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay
can be adjusted in 1-bit increments from 0 to 7 bits.
The BIDR0 to BIDR7 registers are configured as follows:
13.4.1
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7 3/4 bit periods forward, with resolution of 1/4 bit
period. The default sampling point is at the 3/4 bit location.
This can be described as: no. of bits delay = BID[4:0] / 4
For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 *
When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2]
refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from 1/4 to 4/4 in 1/4 bit increments.
(where n = 0 to 7)
Backplane Input Bit Delay Registers (BIDR0 to BIDR7)
BIDRn Bit
Backplane Input Delay Bits 4-0 (BID[4:0])
15:5
4:0
H
to 006A
Table 15 - Backplane Input Bit Delay Register (BIDRn) Bits
H
Reserved
BID[4:0]
Name
Reset
Value
Zarlink Semiconductor Inc.
0
0
ZL50052
Reserved
Must be set to 0 for normal operation
Backplane Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these bits
refers to the input bit fractional delay value (0 to 7 3/4).
When SMPL_MODE = HIGH, the binary value of BID[1:0]
refers to the input bit sampling point (1/4 to 4/4). BID[4:2]
refers to the integer bit delay value (0 to 7 bits).
39
1
/
4
= 4
3
Description
/
4.
Data Sheet