zl50052 Zarlink Semiconductor, zl50052 Datasheet - Page 31

• Manufacturer Part Number: zl50052
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 32 Mbps , And 16 Inputs And 16 Outputs
• Manufacturer: Zarlink Semiconductor

12.0
When the most significant bit, A14, of the address bus is set to ’0’, the microprocessor is performing an access to
one of the device’s internal registers. Address bits A13-A0 indicate which particular register is being accessed.
12:9
8:0
Bit
13
00A3
0023
0063
0083
A14-A0
014D
3FFF
0000
0001
H
H
H
H
Internal Register Mappings
BSAB[3:0]
BCAB[8:0]
- 006A
- 008A
- 002A
- 00AA
Name
H
H
H
H
BE
H
H
H
H
Control Register, CR
Block Programming Register, BPR
Local Input Bit Delay Register 0 - 7, LIDR0 - 7
Backplane Input Bit Delay Register 0 - 7, BIDR0 - 7
Local Output Advancement Register 0 - 7, LOAR0 - 7
Backplane Output Advancement Register 0 - 7, BOAR0 - 7
Memory BIST Register, MBISTR
Device Identification Register, DIR
Backplane Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the BORS pin.
When HIGH, the channel is active.
Source Stream Address Bits
The binary value of these 4 bits represents the input stream number.
Ignored when BMM is set HIGH.
Source Channel Address Bits / Message Mode Data
The binary value of these 9 bits represents the input channel number, when BMM is LOW.
Bits BCAB[7:0] transmitted as data when BMM is set HIGH.
Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits
are output sequentially to the timeslot with BCAB[7] being output first.
Table 9 - BCM Bits for Source-to-Backplane Switching
Table 10 - Address Map for Registers (A14 = 0)
Zarlink Semiconductor Inc.
ZL50052
31
Description
Register
Data Sheet