zl50052 Zarlink Semiconductor, zl50052 Datasheet - Page 20

• Manufacturer Part Number: zl50052
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 32 Mbps , And 16 Inputs And 16 Outputs
• Manufacturer: Zarlink Semiconductor

3.2
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with
respect to the frame boundary FP8o. Each output stream has its own advancement value that can be programmed
by the Output Advancement Registers. The output advancement selection is useful in compensating for various
parasitic loading on the serial data output pins.
The Local and Backplane Output Advancement Registers, LOAR0 - LOAR7 and BOAR0 - BOAR7, are used to
control the Local and Backplane output advancement respectively. The advancement is determined with reference
to the internal system clock rate (131.072 MHz). The advancement can be 0, -1 cycle, -2 cycles or -3 cycles, which
converts to approximately 0 ns, -7.6 ns, -15 ns or -23 ns as shown in Figure 10.
BID[4:0]/LID[4:0] = 00000
SMPL_MODE = HIGH
BID[4:0]/LID[4:0] = 00000
BID[4:0]/LID[4:0] = 00011
BID[4:0]/LID[4:0] = 00011
Bit delay = 0 bit (Default)
SMPL_MODE = LOW
Figure 9 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for
3/4 sampling (Default)
Output Advancement Programming (Backplane and Local Output Streams)
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
Bit Delay = 3/4 bit
2/4 sampling
BSTi/LSTi0-7
BSTi/LSTi0-7
BSTi/LSTi0-7
BSTi/LSTi0-7
FP8i
FP8i
C8i
C8i
B
B
B
B
1
1
1
Ch511
Ch511
Ch511
Ch511
1
0
0
0
Zarlink Semiconductor Inc.
Data Rate of 32 Mbps
ZL50052
0
7
7
7
20
sample at 2/4 point
sample at 3/4 point
sample at 3/4 point
7
6
6
6
Ch0
Ch0
Ch0
sample at 3/4 point
Ch0
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
Data Sheet
2