am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 18

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

1-492
IRQ15/APCS
Address PROM Chip Select
When programmed as APCS in Plug and Play Register
F0, this signal is asserted when the external Address
PROM is read. When an I/O read operation is per-
formed on the first 16 bytes in the PCnet-ISA
controller’s I/O space, APCS is asserted. The outputs of
the external Address PROM drive the PROM Data Bus.
The PCnet-ISA
PROM data bus and drives them on the lower eight bits
of the System Data Bus.
When programmed to IRQ15 (default), this pin has the
same function as IRQ 3, 4, 5, 9, 10, 11, or 12.
BPCS
Boot PROM Chip Select
This signal is asserted when the Boot PROM is read. If
SA0-19 lines match a predefined address block and
MEMR is active and REF inactive, the BPCS signal will
be asserted. The outputs of the external Boot PROM
drive the PROM Data Bus. The PCnet-ISA
buffers the contents of the PROM data bus and drives
them on the lower eight bits of the System Data Bus.
DXCVR/EAR
Disable Transceiver/
External Address Reject
This pin disables the transceiver. The DXCVR output is
configured in the initialization sequence. A HIGH level
indicates the Twisted Pair port is active and the AUI port
is inactive, or SLEEP mode has been entered. A LOW
level indicates the AUI port is active and the Twisted Pair
port is inactive.
If EADI mode is selected, this pin becomes the EAR
input.
The incoming frame will be checked against the inter-
nally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR pin. The EAR pin is defined as REJECT. (See the
EADI section for details regarding the function and tim-
ing of this signal.)
LED0-3
LED Drivers
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section The ISA
Bus Configuration Registers ) and they are active LOW.
When EADI mode is selected, the pins named LED1,
LED2, and LED3 change in function while LED0 contin-
ues to indicate 10BASE-T Link Status.
AMD
LED
1
2
3
+
controller buffers the contents of the
EADI Function
Output
Output
Input/Output
Output
SRDCLK
SF/BD
SRD
+
controller
P R E L I M I N A R Y
Am79C961
+
PRDB3-7
Private Data Bus
This is the data bus for the Boot PROM and the Address
PROM.
PRDB2/EEDO
Private data bus bit 2/Data Out Input/Output
A multifunction pin which serves as PRDB2 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become DATA OUT from the EEPROM.
PRDB1/EEDI
Private data bus bit 1/Data In
A multifunction pin which serves as PRDB1 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become DATA In to the EEPROM.
PRDB0/EESK
Private data bus bit 0/
Serial Clock
A multifunction pin which serves as PRDB0 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become Serial Clock to the EEPROM.
SHFBUSY
An output from PCnet-ISA
from the external EEPROM is in progress. It is active
only when the hardware reconfigure is running (when
data is being shifted out of the EEPROM due to a hard-
ware RESET or the EELOAD command being issued).
This pin should have a pull-up resistor (10 K ) to VCC.
EECS
EEPROM CHIPSELECT
This signal is asserted when read or write accesses are
being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
SLEEP
Sleep
When SLEEP pin is asserted (active LOW), the
PCnet-ISA
and proceeds into a power savings mode. All outputs
will be placed in their normal reset condition. All
PCnet-ISA
the SLEEP pin itself. Deassertion of SLEEP results in
wake-up. The system must delay the starting of the net-
work controller by 0.5 seconds to allow internal analog
circuits to stabilize.
XTAL1
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on External
Crystal Characteristics for more details.
XTAL2
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
+
+
controller performs an internal system reset
controller inputs will be ignored except for
+
which indicates that a read
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input
Input
Output