am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 61

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

prior to the receive message completion, which could be
as short as 12 byte times (assuming 6 bytes for source
To allow simple serial to parallel conversion, SF/BD is
provided as a strobe and/or marker to indicate the de-
lineation of bytes, subsequent to the SFD. This provides
a mechanism to allow not only capture and/or decoding
of the physical or logical (group) address, it also facili-
tates the capture of header information to determine
protocol and or inter-networking information. The EAR
pin is driven LOW by the external address comparison
logic to reject the frame.
If an internal address match is detected by comparison
with either the Physical or Logical Address field, the
frame will be accepted regardless of the condition of
EAR. Incoming frames which do not pass the internal
address comparison will continue to be received. This
allows approximately 58 byte times after the last desti-
nation address bit is available to generate the EAR
signal, assuming the device is not configured to accept
runt packets. EAR will be ignored after 64 byte times af-
ter the SFD, and the frame will be accepted if EAR has
not been asserted before this time. If Runt Packet Ac-
cept is configured, the EAR signal must be generated
PROM
1
0
0
EAR
X
1
0
No timing requirements
No timing requirements
Low for 200 ns within 512 bits after SFD
Internal/External Address Recognition Capabilities
Required Timing
P R E L I M I N A R Y
Am79C961
address, 2 bytes for length, no data, 4 bytes for FCS)
after the last bit of the destination address is available.
EAR must have a pulse width of at least 200 ns.
Note that setting the PROM bit (CSR15, bit 15) will
cause all receive frames to be received, regardless of
the state of the EAR input.
If the DRCUPA bit (CSR15.B) is set and the logical
address (LADRF) is set to zero, only frames which are
not rejected by EAR will be received.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
set). This situation is useful as a power down mode in
that the PCnet-ISA+ controller will not perform any DMA
operations; this saves power by not utilizing the ISA bus
driver circuits. However, external circuitry could still re-
spond to specific frames on the network to facilitate
remote node control.
The table below summarizes the operation of the EADI
features.
All Received Frames
All Received Frames
Physical/Logical Matches
Received Messages
AMD
1-535