am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 89

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

CSR86: Buffer Byte Counter
Bit
15-12
11-0 DMABC
CSR88-89: Chip ID
Bit
31-28
27-12
11-1
0
CSR92: Ring Length Conversion
Bit
15-0
RCON
Name
Name
Name
RES
Register by issuing increment
commands to increment the
memory address for sequential
operations. The DMABA register
is
PCnet-ISA
operation.
This register has meaning only if
the PCnet-ISA
Bus Master Mode.
Read/write accessible only when
STOP bit is set.
Reserved, Read and written with
ones.
DMA Byte Count Register. Con-
tains the Two’s complement of
the current size of the remaining
transmit or receive buffer in
bytes. This register is incre-
mented by the Bus Interface Unit.
The DMABC register is unde-
fined until written.
Read/write accessible only when
STOP bit is set.
Version. This 4-bit pattern is sili-
con revision dependent.
Part number. The 16-bit code for
the PCnet-ISA
0010001001100000b.
Manufacturer ID. The 11-bit
manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
Always a logic 1.
This register is exactly the same
as the Chip ID register in the
JTAG description.
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an en-
coded value as found in the
initialization block to a Two’s
complement value used for inter-
nal counting. By writing bits
15–12 with an encoded ring
undefined
Description
Description
Description
+
controller
+
+
until
controller is in
controller is
the
P R E L I M I N A R Y
DMA
first
Am79C961
CSR94: Transmit Time Domain Reflectometry
Bit
15-10
9-0
CSR96-97: Bus Interface Scratch Register 0
Bit
31-0
CSR98-99: Bus Interface Scratch Register 1
Bit
31-0
CSR104-105: SWAP
Bit
31-0
XMTTDR
SWAP
SCR0
SCR1
Name
Name
Name
Name
RES
Count
length, a Two’s complemented
value is read. The RCON register
is undefined until written.
Read/write accessible only when
STOP bit is set.
Reserved locations. Read and
written as zero.
Time Domain Reflectometry re-
flects the state of an internal
counter that counts from the start
of transmission to the occurrence
of loss of carrier. TDR is incre-
mented at a rate of 10 MHz.
Read accessible only when
STOP bit is set. Write operations
are ignored. XMTTDR is cleared
by RESET.
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers. The SCR0
register is undefined until written.
Read/write accessible only when
STOP bit is set.
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers.
Read/write accessible only when
STOP bit is set.
This register performs word and
byte swapping depending upon if
Description
Description
Description
Description
AMD
1-563