am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 71

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

basically collisions within the slot time with automatic re-
try. The PCnet-ISA+ controller will ensure that collisions
which occur within 512 bit times from the start of trans-
mission (including preamble) will be automatically
retried with no host intervention. The transmit FIFO en-
sures this by guaranteeing that data contained within
the FIFO will not be overwritten until at least 64 bytes
(512 bits) of data have been successfully transmitted
onto the network.
Abnormal network conditions include:
These should not occur on a correctly configured 802.3
network, and will be reported if they do.
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be reset until the STP (the next frame)
is found.
Loss of Carrier
A loss of carrier condition will be reported if the
PCnet-ISA
while it is transmitting on the AUI port. After the
PCnet-ISA
expect to see data “looped back” on the DI pair. This
will internally generate a “carrier sense,” indicating that
the integrity of the data path to and from the MAU is in-
tact, and that the MAU is operating correctly. This
“carrier sense” signal must be asserted before the end
of the transmission. If “carrier sense” does not become
active in response to the data transmission, or becomes
inactive before the end of transmission, the loss of car-
rier (LCAR) error bit will be set in TMD2 after the frame
has been transmitted. The frame will not be re-tried on
the basis of an LCAR error. In 10BASE-T mode LCAR
will indicate that Jabber or Link Fail state has occurred.
Late Collision
A late collision will be reported if a collision condition oc-
curs after one slot time (512 bit times) after the transmit
process was initiated (first bit of preamble commenced).
Loss of carrier
Late collision
SQE Test Error (Does not apply to 10BASE-T
port.)
+
+
controller cannot observe receive activity
controller initiates a transmission, it will
1010....1010
Preamble
Bits
56
10101011
SYNC
Bits
8
ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
ADDR
Bytes
Dest.
6
P R E L I M I N A R Y
Am79C961
ADDR.
Srce.
Bytes
6
If 16 total attempts (initial attempt plus 15 retries) fail, the
PCnet-ISA
transmit TDTE in host memory (TMD2), gives up owner-
ship (sets the OWN bit to zero) for this packet, and
processes the next packet in the transmit ring for trans-
mission.
The PCnet-ISA
process for the particular frame, set Late Collision
(LCOL) in the associated TMD3, and process the next
transmit frame in the ring. Frames experiencing a late
collision will not be re-tried. Recovery from this condition
must be performed by upper-layer software.
SQE Test Error
During the inter packet gap time following the comple-
tion of a transmitted message, the AUI CI
asserted by some transceivers as a self-test. The inte-
gral Manchester Encoder/Decoder will expect the SQE
Test Message (nominal 10 MHz sequence) to be re-
turned via the CI pair within a 40 network bit time period
after DI pair goes inactive. If the CI inputs are not
asserted within the 40 network bit time period following
the completion of transmission, then the PCnet-ISA+
controller will set the CERR bit in CSR0. CERR will be
asserted in 10BASE-T mode after transmit if T-MAU is
in Link Fail state. CERR will never cause INTR to be acti-
vated. It will, however, set the ERR bit in CSR0.
Host related transmit exception conditions include
BUFF and UFLO as described in the Transmit Descrip-
tor section.
Receive Operation
The receive operation and features of the PCnet-ISA
controller are controlled by programmable options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4; this can provide flexibility in
the reception of messages using the 802.3 frame
format.
Length
Bytes
2
+
controller sets the RTRY bit in the current
+
Data
controller will abandon the transmit
LLC
46-1500
Bytes
Pad
18183B-19
16907B-12
FCS
Bytes
4
AMD
pair is
1-545
+