s71gl128nb0 Meet Spansion Inc., s71gl128nb0 Datasheet - Page 127

• Manufacturer Part Number: s71gl128nb0
• Description: Stacked Multi-chip Product Mcp 512/256/128 Megabit 32/16/8 M X 16-bit Cmos 3.0 Volt-only Mirrorbittm Page-mode Flash Memory With 32 Megabit 2m X 16-bit Psram
• Manufacturer: Meet Spansion Inc.

pSRAM Type 7
16Mb (1M word x 16-bit)
32Mb (2M word x 16-bit)
64Mb (4M word x 16-bit)
CMOS 1M/2M/4M-Word x 16 bit Fast Cycle Random Access Memory with Low
Power SRAM Interface
Features
Pin Description
May 4, 2004 pSRAM_Type07_13_A0
Pin Name
A
DQ
21
DQ
CE1#
CE2#
WE#
OE#
UB#
LB#
V
Asynchronous SRAM Interface
Fast Access Time
— tCE = tAA = 60ns max (16M)
— tCE = tAA = 65ns max (32M/64M)
8 words Page Access Capability
— tPAA = 20ns max (32M/64M)
Low Voltage Operating Condition
— VDD = +2.7V to +3.1V
Wide Operating Temperature
— TA = -30°C to +85°C
Byte Control by LB and UB
Low Power Consumption
— IDDA1 = 20mA max (16M)
— IDDA1 = 30mA max (32M)
— IDDA1 =TBDmA max (64M)
— IDDS1 = 100µA max (16M)
— IDDS1 = 80µA max (32M)
— IDDS1 = TBDµA max (64M)
Various Power Down mode
— Sleep, 4M-bit Partial or 8M-bit Partial (32M)
— Sleep, 8M-bit Partial or 16M-bit Partial (64M
DD
to A
16
8
-
-
1
9
0
A d v a n c e
Address Input : A
Chip Enable (Low Active)
Chip Enable (High Active)
Write Enable (Low Active)
Output Enable (Low Active)
Upper Byte Control (Low Active)
Lower Byte Control (Low Active)
Upper Byte Data Input/Output
Lower Byte Data Input/Output
Power Supply
I n f o r m a t i o n
19
pSRAM Type 7
to A
0
for 16M, A
Description
20
to A
0
for 32M, A
21
to A
0
for 64M
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