s71gl128nb0 Meet Spansion Inc., s71gl128nb0 Datasheet - Page 145

• Manufacturer Part Number: s71gl128nb0
• Description: Stacked Multi-chip Product Mcp 512/256/128 Megabit 32/16/8 M X 16-bit Cmos 3.0 Volt-only Mirrorbittm Page-mode Flash Memory With 32 Megabit 2m X 16-bit Psram
• Manufacturer: Meet Spansion Inc.

Note: The t
Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and
Power-Down program was not performed prior to this reset.
Note: Both t
t
May 4, 2004 pSRAM_Type07_13_A0
RC
(min) period for Standby mode from CE1# Low to High transition.
CE2
CE1#
DQ
CE2
CE1#
CE1#
OE#
WE#
V
DD
CHH
CHOX
specifies after V
and t
0V
CHWX
Active (Read)
Power Down Entry
A d v a n c e
define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
Figure 51. Standby Entry Timing after Read or Write
t
DD
CSP
Figure 50. Power Down Entry and Exit Timing
reaches specified minimum level and applicable to both CE1# and CE2.
V
t
CHOX
DD
min
Figure 49. Power-up Timing #2
I n f o r m a t i o n
Standby
Power Down Mode
pSRAM Type 7
High-Z
t
C2LP
t
CHH
t
CHS
Active (Write)
Power Down Exit
t
CHWX
t
CHH
(t
CHHP
)
Standby
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