s71gl128nb0 Meet Spansion Inc., s71gl128nb0 Datasheet - Page 45

• Manufacturer Part Number: s71gl128nb0
• Description: Stacked Multi-chip Product Mcp 512/256/128 Megabit 32/16/8 M X 16-bit Cmos 3.0 Volt-only Mirrorbittm Page-mode Flash Memory With 32 Megabit 2m X 16-bit Psram
• Manufacturer: Meet Spansion Inc.

Common Flash Memory Interface (CFI)
June 14, 2004 S29GLxxxN_00_A4
Write Protect (WP#)
Hardware Data Protection
shipped from the factory with the Secured Silicon Sector permanently locked.
Contact your sales representative for details on using the ExpressFlash service.
The Write Protect function provides a hardware method of protecting the first or
last sector group without using V
by the WP#/ACC input.
If the system asserts V
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected using the method described in“Ad-
vanced Sector Protection” section on page 38. Note that if WP#/ACC is at V
when the device is in the standby mode, the maximum input load current is in-
creased. See the table in “DC Characteristics” section on page 78.
If the system asserts V
whether the first or last sector was previously set to be protected or un-
protected using the method described in “Sector Group Protection and
Unprotection”. Note that WP# has an internal pullup; when uncon-
nected, WP# is at V
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Tables
command definitions). In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V
transitions, or from system noise.
Low V
When V
tects data during V
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V
must provide the proper signals to the control pins to prevent unintentional writes
when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
V
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
IH
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
CC
CC
CC
is less than V
is greater than V
A d v a n c e
Write Inhibit
IL
CC
and OE# = V
IH
power-up and power-down. The command register and all
IL
LKO
S29GLxxxN MirrorBit
.
on the WP#/ACC pin, the device disables program and
, the device does not accept any write cycles. This pro-
LKO
IH
I n f o r m a t i o n
on the WP#/ACC pin, the device reverts to
.
ID
IH
. Write Protect is one of two functions provided
during power up, the device does not accept
TM
CC
Flash Family
is greater than V
CC
power-up and power-down
IL
, CE# = V
LKO
16
. The system
IH
and
or WE# =
17
for
IL
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