txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 4

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

BLOCK DIAGRAM DESCRIPTION
A simplified block diagram of the L4M device is shown in Figure 1. A byte-wide or nibble-wide 139.264 Mbit/s
signal (TXDn) is connected to the Input Block. The nibble interface is selected by placing a high on the lead
designated as NIB. Data is clocked into the L4M on positive transitions of the clock signal TXC. A control bit is
provided which enables data to be clocked into the L4M on negative transitions of the clock. The L4M Input
Block also terminates an external loss of signal (EXLOS) indication. A low placed on this lead indicates that an
external line interface device, such as a CMI interface device, has detected a loss of signal. This signal is
reported as an alarm within the L4M for the microprocessor, and can generate an interrupt and a 140 Mbit/s
AIS when enabled.
The 140 Mbit/s transmit line signal is monitored by the two Transmit Performance Monitoring Blocks for ITU-T
G.751 frame alignment and a Distant Alarm Status. A Distant Alarm is defined as a 1 in bit 13 of the G.751
frame format. This alarm can generate an interrupt indication when enabled. When frame alignment is estab-
lished, framing errors are counted in a 16-bit performance counter. The 140 Mbit/s line signal is also monitored
for an Alarm Indication Signal (AIS). The AIS detection circuit can be enabled to work in conjunction with the
frame alignment circuit. An AIS condition is reported as an alarm, and can generate an interrupt when enabled.
The Stuff/Sync Block contains a FIFO and is controlled by write timing from the Input Block, and by read timing
from the Build Block. The FIFO accommodates input and timing jitter as specified in ITU-T Recommendation
G.823. The FIFO is protected against overflow and underflow conditions by reporting a FIFO error alarm, and
will automatically recenter when a FIFO underflow or overflow alarm has been detected. The reset is held for
approximately one frame before the FIFO is released for operation. Upon power-up, or on applying a reset, the
transmit FIFO is also recentered. The stuffing algorithm uses one set of five control bits (C-bits) with one stuff
opportunity bit (S-bit) per subframe (nine subframes) for frequency justification.
The Build Block, with timing signals exchanged with the Stuff/Sync Block, constructs the VC-4 format as illus-
trated below.
The L4M can build the 261 column by 9 row VC-4 format without or with path overhead bytes, and "O"-bits,
depending on the features selected. The addition of POH bytes to the VC-4 format is disabled by applying a
low to the pin designated POHDIS (also applying a low to POHDIS disables receive VC-4 POH processing).
The starting position of the VC-4 J1 bytes can be synchronized to the add bus J1 pulse, when add bus timing
is selected, or have a starting location of 0 or 522, when drop bus or the external timing modes are selected.
The L4M can also generate an unequipped or supervisory unequipped VC-4. An unequipped VC-4 is defined
as all zeros for the POH and payload bytes, while a supervisory unequipped VC-4 is defined as having valid
POH bytes, but the payload bytes equal to zero. The Build Block is also responsible for multiplexing individual
1
9
J1
O
POH
P
H
1
W
X
Y
Y
139.264 Mbit/s Build Format
96I
96I
96I
96I
X
Y
Y
Y
96I
96I
96I
96I
Subframe 1
Subframe 2
Subframe 9
Y
Y
Y
X
96I
96I
96I
96I
Y
Y
X
Y
96I
96I
96I
96I
DATA SHEET
- 4 -
Y
X
Y
Z
96I
96I
96I
96I
261
R: Fixed Stuff Bits
C: Justification Control Bits
S: Justification Opportunity Bits
O: Overhead Bits
W = I I I I I I I I
X = C R R R R R O O
Y = R R R R R R R R
Z = I I I I I I S R
I: Information Bits
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M