txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 79

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

STATUS REGISTER BIT DESCRIPTIONS
The unlatched alarms are allocated to even numbered hexadecimal address locations, while the latched alarm
bit positions are allocated to odd numbered register locations. A latched bit sets on the positive level of the
alarm. A latched bit position clears on a microprocessor read cycle. If the alarm is active after the read cycle,
the bit position will relatch.
Address
20
21
Bit
7
6
5
4
3
2
1
0
ABLOJ1
DBLOJ1
Symbol
ANOOL
TLAISD
TFIFOE
LAISC
E1AIS
XAIS
Analyzer Out Of Lock: When enabled, an alarm occurs when the 2
analyzer is out of lock. An out of lock alarm occurs when 30 bits in a 1000
bits are received in error. In lock occurs when the first 24 bits in the pattern
are received correctly. An out of lock disables the analyzer error 16-bit
counter. This bit is forced to 0 when the ANAEN control bit is set to 0.
Transmit Line AIS Detected: An alarm occurs when a 140 Mbit/s AIS has
been detected (all ones in the transmit bit stream). When control bit FDAEN
is a 0, an AIS is detected when the incoming signal has five or less zeros in
each of two consecutive frame periods (2928 bits per frame). Recovery
occurs when if each of two consecutive frame periods contains six or more
zeros. When control bit FDAEN is a 1, AIS is detected when the incoming
signal has five or less zeros in each of two consecutive frame periods, and a
loss of frame alignment has been detected. Recovery occurs when each of
two consecutive frame periods contains six or more zeros, or frame align-
ment has occurred. Other than reporting the alarm, no action is taken.
Transmit FIFO Error Detected: An alarm occurs when an overflow or
underflow condition has taken place in the transmit FIFO. The FIFO
recenters automatically after the FIFO error. Other than reporting the alarm,
and recentering the FIFO, no action is taken.
Add Bus Loss of J1: An alarm occurs when, in add bus timing mode, the J1
pulse in the AC1J1 signal is missing for 8 consecutive frames. Recovery
occurs when the J1 pulse in the AC1J1 signal is present for 8 consecutive
frames.
Loss of AIS Clock: An alarm occurs when the AIS input clock (AISCK) is
stuck high or low for 12-34 consecutive clock cycles of the RAM clock
(RAMCI). Recovery occurs on the first clock transition. This clock is used to
generate the 140 Mbit/s line AIS when control bit BSAISE is a 0.
External AIS Indication: An indication occurs when an active low is present
on the EXAIS pin. When control bit RAISEN is a 1, a receive 140 Mbit/s AIS
is generated, and a path RDI is generated when RDIEN=1.
Drop Bus Loss of J1: An alarm occurs when the J1 pulse in the DC1J1 sig-
nal is missing for 8 consecutive frames. Recovery occurs when the J1 pulse
in the DC1J1 pulse is present for 8 consecutive frames. When the pointer
tracking feature is enabled (PTEN is high), the detection of this alarm is dis-
abled.
AIS Detected in the E1 Byte: An alarm occurs when a majority of all ones
(5 out of 8 bits are a 1) has been detected in the incoming E1 byte once.
Recovery occurs when a majority of ones is not detected once. This provides
a means of signaling the 140 Mbit/s Mapper that an upstream SDH/SONET
Loss Of Frame and other alarms have occurred.
DATA SHEET
- 79 -
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
23
-1
L4M