txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 45

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Receive C2 Byte
The L4M provides C2 signal label mismatch detection between the received C2 byte, and a microprocessor-
written value and also a fixed 01H value in hardware, when enabled. When control bit C2FVD is written with a
1, the detection of the 01 value is disabled, and detection depends solely on the register value written by the
microprocessor. Five or more consecutive mismatched signal labels in the C2 byte from the microprocessor-
written value or a label not equal to the 01H (when C2FVD=0) results in a path signal label error (PSLERR)
alarm. The alarm state is exited when five or more consecutive matches, or the 01H value (when C2FVD=0)
are received correctly.
The L4M also provides an unequipped indication (C2EQ0) when the incoming C2 byte matches an internal
00H value for five consecutive frames. The alarm is exited when the C2 byte does not equal a 00H value for
five or more consecutive frames. Please note that if the accepted path signal label value is all zeros (C2
unequipped), or an 01 (if C2FVD=0), a mismatch alarm (PSLERR) is not declared.
The C2 mismatch detection and unequipped indication are disabled when any of the following alarms are
detected.
Receive G1 Byte
The received states of the G1 byte are provided for a microprocessor read cycle, and are also provided at the
path overhead byte interface, for external processing as required.
Bits 1 through 4 in the G1 byte convey a FEBE count. There are nine possible valid FEBE values, 0 through 8.
Other values are detected as a zero count. The FEBE value received is the count of interleaved bit blocks that
have been detected in error in the received Path BIP-8 code at the far end. A 16-bit counter is provided for
counting the number of FEBE bits or blocks received in error. Up to eight errors per frame may be counted.
Bit 5 is the defined as the Path Far End Receive Defect Indication alarm (Path RDI) indication. A receive path
RDI alarm indication (RRDI) occurs when the L4M detects a one for five or ten consecutive frames. Recovery
occurs when the L4M detects a zero for five or ten consecutive frames. Writing a 1 to control bit RDI10 selects
the detect and recovery value of 10 consecutive events.
Bits 6, 7, and 8 in the G1 byte are unassigned and are normally received as 0s. They are provided for both a
microprocessor read cycle and at the external POH interface.
Receive Desynchronizer
The rate at which the pointer leak buffer is to be leaked is written to the 15-bit pointer leak rate register.
If enhanced desynchronizer operation is required, the following additional signals are provided: a stuff indica-
tion lead, positive and negative justification indications, and a pointer leak counter equal to zero indication lead.
For controls, a LOADEN control bit and a 9-bit (plus sign bit) pointer offset counter are provided, in addition to
the 15-bit pointer leak rate register.
- Loss of Drop Bus J1 Pulse (DBLOJ1) when the PTEN pin is low
- E1 AIS (E1AIS) (from the Drop bus) when EAPE is 0
- ISTAT is a 1 when EAPE is 1
- PAIS is a 1 when EAPE is 1
- Receive loss of pointer (RLOP) when the PTEN pin is high
- Receive path AIS (RPAIS) when the PTEN pin is high
DATA SHEET
- 45 -
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M