txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 50

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Performance Counters
All 16-bit performance counters have a special 16-bit read operation which allows uninterrupted access, with-
out the danger of one byte changing while the other byte is read. To perform a 16-bit read operation, the low
order byte is read first. The read operation freezes the count in the high order byte. The high order byte should
be read next.
All the performance counters can also be configured to be either saturating or non-saturating. When a 0 is writ-
ten to control bit COR (bit 0 in 13H), the performance counters are configured to be saturating, with the
counters stopping at their maximum count. An 8-bit or 16-bit counter is reset on a microprocessor read cycle.
Counts that occur during the read cycle are held, and the counter updated afterwards. When a 1 is written to
control bit COR, the performance counters are configured to be non-saturating, and roll over after the maxi-
mum count in the counter is reached. In this mode, the counters do not clear on a microprocessor read cycle,
but continue to count.
All the performance counters can be reset simultaneously by writing a 1 to control bit RSETC (bit 7 in 1CH).
This bit is self clearing, and does not require the microprocessor to write a 0 into this location afterwards. In
addition, a performance counter can also be cleared by writing the value of 00H to the low byte, immediately
followed by writing a 00H to address n+1. The n+1 address location contains the high order byte of the 16-bit
performance counter.
All performance counters (except the Receive Framing Error counter and the Transmit Framing Error counter)
are inhibited when any of the following alarms occur, and released for operation after the last alarm clears.
The receive framing counters and transmit framing counters are inhibited on loss of frame alignment.
- Loss of Drop Bus J1 pulse (DBLOJ1) when PTEN pin is low.
- Receive loss of pointer alarm (RLOP) when PTEN pin is high.
- Receive path AIS alarm (RPAIS) when PTEN pin is high.
- Loss of Drop Bus Clock (DBLOC).
- E1 byte AIS Detected (E1AIS) when external alarm enable (EAPE)
- External alarm ISTAT pin is high (XISTAT) when external alarm enable
- External alarm PAIS pin is high (XPAIS) when external alarm enable
- J1 loss of lock (J1LOL) alarm and control bit J1LEN is a 1
- J1 trace identifier mismatch (J1TIM) alarm and control bit J1TEN is a 1
- Received active low on the external AIS lead (XAIS alarm).
- Path Signal Label Enable control bit (PSLER) is a 1, and either a
control bit is 0.
(EAPE) control bit is 1.
(EAPE) control bit is 1.
(and POHDIS is a 1).
(and POHDIS is a 1).
PSLERR or C2EQ0 alarm occurs.
DATA SHEET
- 50 -
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M