txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 76

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Address
1A
1B
18
19
18
7-4
7-0
7-0
7-1
Bit
3
2
1
0
Pointer Leak
C1 Offset
FEBEBC
Register
Symbol
Receive
RC1DC
RDI10
PADS
Rate
Receive C1 Offset Register: Enabled when a high is placed on the
pointer tracking machine control lead PTEN (pin 2), and when control bit
RC1DC is a 1. The 12-bit register location compensates the position of
the C1 pulse in the DC1J1 or DC1 signal (pin 127, 126). The LSB is bit 0
in 19H, and the MSB is bit 7 in 18H. The register compensates for up to
2429 (270 columns X 9 rows - 1). For example, if the C1 pulse is in the
correct position, zeros are written to the register. The correct position of
the framing reference is when C1 corresponds to the C11 position in the
SDH/SONET format. When a binary 1 is written to the register (bit 0 in
19H is a 1), it is assumed that the position of the C1 pulse present in the
DC1 signal is shifted in time one byte and the input pulse corresponds to
the C12 byte position in the SDH/SONET frame. This means that the
starting point for the frame should be one byte earlier. Values written into
the register greater than a binary value of 2429 will be counted as zero
delay.
Receive C1 Delay Control: Enabled when the pointer tacking machine
is selected, when a high is placed on PTEN (pin 2). A 1 enables the
receive 12-bit register in locations 18 and 19H to compensate for a C1
offset delay in the receive direction.
RDI/FERF Recovery/Detection 10 Consecutive Enable: A 1 selects
10 consecutive events as the value for detection and recovery. A 0
selects 5 consecutive events as the value for detection and recovery.
Pointer Tracking Machine AIS to LOP Transition Disabled: A 1 dis-
ables the AIS to LOP transition in the pointer tracking state machine. A 0
enables the AIS to LOP transition in the pointer tracking machine.
FEBE Block Count Enable: A 1 enables the FEBE counter to be con-
figured to count FEBE blocks instead of FEBES. A valid count (between
1 and 8) will increment the 16-bit counter once. A 0 configures the FEBE
counter to count FEBES.
FIFO Leak Rate Register: The 15-bit value written into registers 1A and
1BH is used for presetting the internal pointer leak counter. The value
written into this register is based on the rate of occurrence of pointer
movements from the number of counts read from positive/negative stuff
counters, and the NJ/PJ indication pins. This count will represent the
average leak rate. A count of 1 will decrement the pointer leak counter
every three rows. Thus the minimum time to leak out one pointer move-
ment is 8 frames or 1 millisecond, since each pointer movement is 24
bits. Bit 7 in register 1BH is assigned as the MSB, and represents bit 15
in the string, as shown below:
Bit 7
A pin (PLEQ0) is provided that will give a positive indication when the
pointer leak counter is equal to zero. This indication is reset to zero
when the pointer leak counter is preset. Register 1AH is preset to 01H
after a device reset.
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6
Register 1B
5
DATA SHEET
- 76 -
4
3
2
1
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Description
7
Register 1A
6
5 4
3
2
1
Ed. 1A, January 2000
0
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TXC-03456
TXC-03456-MB
L4M