at52sc1283j ATMEL Corporation, at52sc1283j Datasheet - Page 21

• Manufacturer Part Number: at52sc1283j
• Description: 128-mbit Flash + 32-mbit/64-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

9. Burst Configuration Register
Notes:
10. Clock Latency versus Input Clock Frequency
Figure 10-1. Output Configuration
3530B–STKD–2/4/05
B15
B14
B13 - B11:
B10
B9
B8
B7
B6
B5 - B4
B3
B2 - B0
(Minimum Number of Clocks Following Address Latch)
1. Default State
2. Burst configuration setting of B13 - B11 = 010 (clock latency of two), B9 = 1 (hold data for two clock cycles) and B8 = 1
3. Data is not ready when WAIT is asserted.
(WAIT asserted one clock cycle before data is valid) is not supported.
Minimum Clock Latency
0
1
0
010
011
100
101
110
0
1
0
1
0
1
1
0
1
00
0
1
001
010
011
111
(1)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
5, 6
2, 3
(2)
(1)
(1)
4
Data Hold
Data Hold
(B9 = 0)
(B9 = 1)
1 CLK
2 CLK
I/00 - I/015
I/00 - I/015
CLK
Synchronous Burst Reads Enabled
Asynchronous Reads Enabled
Four-word Page
Clock Latency of Two
Clock Latency of Three
Clock Latency of Four
Clock Latency of Five
Clock Latency of Six
WAIT Signal is Asserted Low
WAIT Signal is Asserted High
Hold Data for One Clock
Hold Data for Two Clocks
WAIT Asserted during Clock Cycle in which Data is Valid
WAIT Asserted One Clock Cycle before Data is Valid
Linear Burst Sequence
Burst Starts and Data Output on Falling Clock Edge
Burst Starts and Data Output on Rising Clock Edge
Reserved for Future Use
Wrap Burst Within Burst length set by B2 - B0
Don’t Wrap Accesses Within Burst Length set by B2 - B0
Four-word Burst
Eight-word Burst
Sixteen-word Burst
Continuous Burst
AT52SC1283J/1284J [Preliminary]
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
Input Clock Frequency
OUTPUT
OUTPUT
VALID
VALID
≤ 66 MHz
≤ 61 MHz
≤ 40 MHz
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