at52sc1283j ATMEL Corporation, at52sc1283j Datasheet - Page 32

• Manufacturer Part Number: at52sc1283j
• Description: 128-mbit Flash + 32-mbit/64-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

24. AC Burst Read Timing Characteristics
25. Burst Read Cycle Waveform
Notes:
32
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
CKH
CKL
CKRT
CKFT
ACK
AVCK
CECK
CKAV
QHCK
AHCK
CKRY
CESAV
AAV
AHAV
CKQV
CEQZ
1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid
2. After the high-to-low transition on AVD, AVD may remain low.
AT52SC1283J/1284J [Preliminary]
line) shown is for a burst configuration setting of B10 = 1 and B8 = 0.
Parameter
CLK Period
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
Address Valid to Clock
AVD Low to Clock
CE Low to Clock
Clock to AVD High
Output Hold from Clock
Address Hold from Clock
Clock to WAIT Delay
CE Setup to AVD
Address Valid to AVD
Address Hold From AVD
CLK to Data Delay
CE High to Output High-Z
I/O0-I/O15
A0-A22
WAIT
AVD
CLK
CE
OE
(2)
(1)
t
t
AVCK
ACK
t
CECK
t
CESAV
t
AAV
t
CKAV
t
AHCK
t
CE
t
AHAV
...
t
QHCK
t
CLK
D13
... D14
...
t
CKRY
t
CKQV
D15
Min
15
10
10
4
4
7
7
7
3
3
8
9
...
D16
t
CKRY
D17
t
CKH
Max
t
CKL
3.5
3.5
t
13
13
10
CEQZ
3530B–STKD–2/4/05
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns