at52sc1283j ATMEL Corporation, at52sc1283j Datasheet - Page 49

• Manufacturer Part Number: at52sc1283j
• Description: 128-mbit Flash + 32-mbit/64-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

52. Low-power Modes
52.1
52.2
52.3
In asynchronous operation mode, the user has the option to toggle A0 - A3 in a random way at higher rate (20 ns vs. 70 ns)
to lower access times of subsequent reads with 16-word boundary. In synchronous mode, this option has no effect. The
maximum page length is 16 words.
Please note that as soon as Page Mode is enabled the CS1 low time restriction applies. This means that the CS1 signal
must not be kept low longer than t
52.4
Note:
3530B–STKD–2/4/05
Note:
A20 - A8 (32M)
A21 - A8 (64M)
Mode Register Set
ZZ Enable/Disable
Page Mode Enable/Disable
MRS Update
The register update takes place on the rising edge of ZZ. Once the register is updated, the next time ZZ goes low, without any
updates to the register starting within the t
care when ZZ is low during the register updates.
If the register is written to enable the Deep Power-down, the part will go into Deep Power-down during the following time that
ZZ is driven low and there is no MRS update. When ZZ is driven high, all of the register settings will return to default state for
the part (i.e. full array refresh, Deep Power-down Disabled).
0
PUB, PLB
Address
Enable/Disable
PCS1
PWE
Page Mode
ZZ
A7
A4
A7
0
1
0
1
RC(
t
WC)
= 10 µs.
ZWE
ZZWE
A6
Register Write Start
1
max time of 1 µs, the part will refresh the array selected. The data bus is a don’t
S
AT52SC1283J/1284J [Preliminary]
W
(2)
C
W
W
P
(1)
A5
1
Page Mode Disabled (Default)
Register Write
Complete
Deep Power-down Enable
DPD Disable (Default)
Page Mode Enabled
Enable/Disable
R
(4)
Register Update
Type
Type
A4
ZZ
Complete
A3 - A0
0
49