at52sc1283j ATMEL Corporation, at52sc1283j Datasheet - Page 33

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at52sc1283j

Manufacturer Part Number
at52sc1283j
Description
128-mbit Flash + 32-mbit/64-mbit Psram Stack Memory
Manufacturer
ATMEL Corporation
Datasheet
26. Burst Read Waveform (Clock Latency of 3)
Note:
27. Hold Data for 2 Clock Cycles Read Waveform (Clock Latency of 3)
Note:
3530B–STKD–2/4/05
1. Dashed line reflects a B10 and B8 setting of 0 in the configuration register. Solid line reflects a B10 setting of 1 and B8
1. Dashed line reflects a burst configuration register setting of B10 and B8 = 1, B9 = 1.
I/O0-I/O15
I/O0-I/O15
setting of 1 in the configuration register.
Solid line reflects a burst configuration register setting of B10 = 1, B9 and B8 = 1
A0-A22
A0-A22
WAIT
WAIT
AVD
CLK
AVD
CLK
CE
OE
CE
OE
(1)
(1)
HIGH Z
VALID
A
A9
B
D13
D13
C
D14
AT52SC1283J/1284J [Preliminary]
D
D14
E
D15
D15
F
D16
G
D17
D18
HIGH Z
D16
33

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