k4s643232c Samsung Semiconductor, Inc., k4s643232c Datasheet - Page 3

• Manufacturer Part Number: k4s643232c
• Description: 2m X 32 Sdram 512k X 32bit X 4 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

K4S643232C
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle
FUNCTIONAL BLOCK DIAGRAM
clock
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
CLK
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
- 3 -
GENERAL DESCRIPTION
Latency & Burst Length
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Programming Register
WE
K4S643232C-TC/L55
K4S643232C-TC/L60
K4S643232C-TC/L70
K4S643232C-TC/L80
K4S643232C-TC/L10
The K4S643232C is 67,108,864 bits synchronous high data
Data Input Register
Column Decoder
512K x 32
512K x 32
512K x 32
512K x 32
Part NO.
DQM
LWCBR
*
Samsung Electronics reserves the right to
change products or specification without
notice.
Max Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
REV. 1.1 Nov. '99
CMOS SDRAM
LDQM
Interface
LVTTL
LWE
LDQM
DQi
Package
TSOP(II)
86