k4s643232c Samsung Semiconductor, Inc., k4s643232c Datasheet - Page 30

• Manufacturer Part Number: k4s643232c
• Description: 2m X 32 Sdram 512k X 32bit X 4 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

DQ
CLOCK
K4S643232C
Page Read Cycle at Different Bank @Burst Length=4
A
ADDR
DQM
10
CKE
RAS
CAS
BA
BA
/AP
WE
CS
CL=2
CL=3
0
1
*Note :
0
*Note 1
Row Active
(A-Bank)
RAa
RAa
1
1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
2
Row Active
(B-Bank)
RBb
RBb
3
(A-Bank)
Read
CAa
4
5
Row Acive
(C-Bank)
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
RCc CBb
RCc
6
(B-Bank)
QAa0 QAa1 QAa2 QBb0
Read
7
Precharge
(A-Bank)
8
Row Active
(D-Bank)
RDd
RDd
9
- 30
(C-Bank)
HIGH
Read
CCc
10
Precharge
(B-Bank)
QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
11
12
(D-Bank)
Read
CDd
13
Precharge
(C-Bank)
14
15
Precharge
(D-Bank)
REV. 1.1 Nov. '99
CMOS SDRAM
16
*Note 2
17
18
: Don't care
19