k4s643232c Samsung Semiconductor, Inc., k4s643232c Datasheet - Page 5

• Manufacturer Part Number: k4s643232c
• Description: 2m X 32 Sdram 512k X 32bit X 4 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

CAPACITANCE
K4S643232C
ABSOLUTE MAXIMUM RATINGS
PIN FUNCTION DESCRIPTION
Note :
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
DQ
Voltage on any pin relative to Vss
Voltage on V
Storage temperature
Power dissipation
Short circuit current
CLK
CS
CKE
A
BA0,1
RAS
CAS
WE
DQM0 ~ 3
DQ
V
V
NC
0
DD
DDQ
0
~ A
0
~ DQ
/V
Pin
~
/V
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
SS
10
31
SSQ
31
Parameter
DD
System clock
Chip select
Clock enable
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No Connection
supply relative to Vss
Pin
(V
DD
Name
= 3.3V, T
A
= 23 C, f = 1MHz, V
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
V
Symbol
V
Symbol
DD
C
C
C
IN
C
T
ADD
OUT
CLK
, V
I
, V
P
IN
STG
OS
D
REF
OUT
DDQ
= 1.4V
0
- 5 -
~ RA
10
SHZ
200 mV)
, Column address : CA
after the clock and masks the output.
Min
2.5
2.5
2.5
4.0
Input Function
-55 ~ +150
-1.0 ~ 4.6
-1.0 ~ 4.6
Value
50
1
0
~ CA
Max
4.5
4.5
6.5
4
7
REV. 1.1 Nov. '99
CMOS SDRAM
Unit
mA
Unit
W
V
V
C
pF
pF
pF
pF