k9f1208u0a-y Samsung Semiconductor, Inc., k9f1208u0a-y Datasheet - Page 35

• Manufacturer Part Number: k9f1208u0a-y
• Description: 64m X 8 Bit , 32m X 16 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

Figure 10. Sequential Row Read2 Operation
K9F1208D0A
K9F1208U0A
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528 bytes(x8 device) or 264words(x16 device), in a single page program cycle. The number of consecutive partial page pro-
gramming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare
array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in
which up to 528 bytes(x8 device) or 264words(x16 device) of data may be loaded into the page register, followed by a non-volatile
programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half
array by moving pointer. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
Figure 11. Program & Read Status Operation
R/B
I/O
R/B
I/O
X
0
~
7
50h
80h
K9F1216D0A
K9F1216U0A
(A
Don’t Care)
Start Add.(4Cycle)
A
4
0
~ A
~ A
A
Address & Data Input
0
528 Byte Data
7
~ A
3
:
& A
7
& A
9
~ A
9
~ A
25
25
t
R
10h
Data Field
Data Output
1st
(only for
35
t
PROG
Spare Field
K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P
t
R
1st
Nth
Data Output
Block
(16Byte)
70h
2nd
FLASH MEMORY
t
R
Fail
I/O
valid within a block)
0
Data Output
(16Byte)
Nth
Pass