m393b1k70bh1 Samsung Semiconductor, Inc., m393b1k70bh1 Datasheet
m393b1k70bh1
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Registered DIMM DDR3 SDRAM Specification 240pin Registered DIMM based on 2Gb B-die 78FBGA with Lead-Free & Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL ...
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... Timing & Capacitance values ............................................................................................................................ 10 9.2 Clock driver Characteristics .............................................................................................................................. 10 10.0 Functional Block Diagram: .................................................................................................................................... 11 10.1 4GB, 512Mx72 Module(Populated as 2 rank of x8 DDR3 SDRAMs) ............................................................. 11 10.2 4GB, 512Mx72 Module(Populated as 1 ranks of x4 DDR3 SDRAMs) ........................................................... 12 10.3 8GB, 1Gx72 Module(Populated as 2 ranks of x4 DDR3 SDRAMs)................................................................ 13 10.4 8GB, 1Gx72 Module(Populated as 4 ranks of x8 DDR3 SDRAMs)................................................................ 15 10 ...
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... Module(2 Ranks) ....................................................................................................... 45 19.3.1 x72 DIMM, populated as one physical ranks of x4 DDR3 SDRAMs.................................................... 45 19.3.2 Heat Spreader Design Guide ................................................................................................................. 46 19.4 256Mbx8 based 1Gx72 Module(4 Ranks) ....................................................................................................... 48 19.4.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs.................................................... 48 19.5 16GB based 2Gx72 Module(4 Ranks)............................................................................................................. 49 19.6.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs.................................................... 49 19 ...
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Registered DIMM Revision History Revision Month Year 1.0 December 2008 - First Release History Rev. 1.0 December 2008 DDR3 SDRAM ...
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... Registered DIMM 1.0 DDR3 Registered DIMM Ordering Information Part Number M393B5273BH1-CF8/H9 M393B5270BH1-CF8/H9 M393B1K70BH1-CF8/H9 M393B1K73BH1-CF7/F8 M393B2K70BM1-CF7/F8 * Note - ## : F7(800Mbps 6-6-6) / F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9) 2.0 Key Features DDR3-800 Speed 6-6-6 tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) 37.5 tRC(min) 52.5 • JEDEC standard 1.5V ± 0.075V Power Supply • 1.5V ± 0.075V DDQ • 400 MHz f ...
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Registered DIMM 4.0 Registered DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back 121 REFDQ 122 DQ4 SS 3 DQ0 123 DQ5 V 4 DQ1 124 SS DM0,DQS9 V 5 125 SS ,TDQS9 ...
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Registered DIMM 5.0 Pin Description Pin Name Description CK0 Clock Input, positive line CK0 Clock Input, negative line CKE[1:0] Clock Enables RAS Row Address Strobe CAS Column Address Strobe WE Write Enable S[3:0] Chip Selects A[9:0],A11, Address Inputs A[15:13] A10/AP ...
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... These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg- ister outputs. ...
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... Connected to DQS on x4 DRAMs, TDQS on x8 153, 162, 204, TDQSn SDRAMs on RDIMMs; (n=9...17) 213, 222, 231 Connected to optional thermal sensing compo- EVENT nent. 187 Modules without a thermal sensing component. Note : internal connection RDIMM Notes ODT1,NC A15, NC NC, CBn DDR3 SDRAM ...
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Registered DIMM 9.0 Registering Clock Driver Specification 9.1 Timing & Capacitance values Symbol Parameter fclock Input Clock Frequency t /t Pulse duration, CK, CK HIGH or LOW Inputs active time4 before RESET is taken HIGH ACT t ...
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... Registered DIMM 10.0 Functional Block Diagram: 10.1 4GB, 512Mx72 Module DQS8 DQS DQS8 DQS DM8/DQS17 TDQS D8 DQS17 TDQS CB[7:0] DQ[7:0] ZQ DQS3 DQS DQS3 DQS DM3/DQS12 TDQS D3 DQS12 TDQS DQ[31:24] DQ[7:0] ZQ DQS2 DQS DQS2 DQS DM2/DQS11 TDQS D2 DQS11 TDQS DQ[23:16] DQ[7:0] ZQ DQS1 DQS DQS1 DQS DM1/DQS10 TDQS D1 DQS10 TDQS DQ[15:8] DQ[7:0] ZQ DQS0 ...
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... Registered DIMM 10.2 4GB, 512Mx72 Module ZQ DQS8 DQS DQS17 DQS8 DQS DQS17 DM VSS D8 DQ[3:0] CB[3:0] CB[7:4] ZQ DQS3 DQS17 DQS DQS3 DQS DQS17 DM VSS D3 DQ[3:0] DQ[27:24] DQ[27:24] DQ[31:28] ZQ DQS8 DQS DQS17 DQS8 DQS DQS17 DM VSS D2 DQ[3:0] DQ[19:16] DQ[19:16] DQ[23:20] ZQ DQS8 DQS17 DQS DQS8 DQS DQS17 DM VSS D1 DQ[3:0] DQ[11:8] DQ[15:12] ZQ DQS8 DQS DQS17 DQS8 ...
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... Registered DIMM 10.3 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) DQS17 DQS DQS17 DQS VSS DM D17 CB[7:4] DQ[3:0] DQS12 DQS DQS12 DQS VSS DM D12 DQ[31:28] DQ[3:0] DQS11 DQS DQS11 DQS VSS DM D11 DQ[23:20] DQ[3:0] DQS10 DQS DQS10 DQS VSS DM D10 DQ[15:12] DQ[3:0] DQS0 DQS DQS0 DQS VSS DM D0 ...
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Registered DIMM DQS14 DQS DQS14 DQS VSS DM D14 CB[47:44] DQ[3:0] DQS4 DQS DQS4 DQS VSS DM D4 DQ[35:32] DQ[3:0] DQS16 DQS DQS16 DQS VSS DM D16 DQ[63:60] DQ[3:0] DQS10 DQS DQS10 DQS VSS DM D7 DQ[59:56] DQ[3:0] Vtt Option ...
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... Registered DIMM 10.4 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) DQS0 DQS DQS DQS0 DQS DQS U0 DQ[7:0] DQ[7:0] DQ[7: DQS1 DQS DQS DQS1 DQS DQS U1 DQ[7:0] DQ[7:0] DQ[15: DQS2 DQS DQS DQS2 DQS DQS U2 DQ[7:0] DQ[7:0] DQ[23:16 DQS3 DQS DQS DQS3 DQS DQS U3 DQ[7:0] DQ[7:0] DQ[31:24 DQS8 DQS ...
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... Registered DIMM 10.5 16GB,2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs) VSS ZQ VSS DQS8 DQS DQS8 DQS VSS DM D9 CB[3:0] DQ[3:0] VSS ZQ VSS DQS3 DQS DQS3 DQS VSS DM D7 DQ[27:24] DQ[3:0] VSS ZQ VSS DQS2 DQS DQS2 DQS VSS DM D5 DQ[19:16] DQ[3:0] VSS ZQ VSS DQS1 DQS DQS1 DQS VSS ...
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Registered DIMM VSS ZQ VSS DQS17 DQS DQS17 DQS VSS DM D27 CB[7:4] DQ[3:0] VSS ZQ VSS DQS12 DQS DQS12 DQS VSS DM D25 DQ[31:28] DQ[3:0] VSS ZQ VSS DQS11 DQS DQS11 DQS VSS DM D23 DQ[23:20] DQ[3:0] VSS ZQ ...
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Registered DIMM VSS ZQ VSS DQS4 DQS DQS4 DQS VSS DM D11 DQ[35:32] DQ[3:0] VSS ZQ VSS DQS5 DQS DQS5 DQS VSS DM D13 DQ[43:40] DQ[3:0] VSS ZQ VSS DQS6 DQS DQS6 DQS VSS DM D15 DQ[51:48] DQ[3:0] VSS ZQ ...
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Registered DIMM VSS ZQ VSS DQS13 DQS DQS13 DQS VSS DM D29 DQ[39:36] DQ[3:0] VSS ZQ VSS DQS14 DQS DQS14 DQS VSS DM D31 DQ[47:44] DQ[3:0] VSS ZQ VSS DQS15 DQS DQS15 DQS VSS DM D33 DQ[55:52] DQ[3:0] VSS ZQ ...
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Registered DIMM S0 ARS0A-> CS1 : SDRAMs D1, D3, D5, D7, D9 D19, D21, D23, D25, D27 ARS0B-> CS1 : SDRAMs D11, D13, D15, D17 D29, D31, D33, D35 S1 ARS1A-> CS0 : SDRAMs D0, D2, D4, D6, D8 D18, ...
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Registered DIMM 11.0 Absolute Maximum Ratings 11.1 Absolute Maximum DC Ratings Symbol Parameter V Voltage on V pin relative to Vss Voltage on V pin relative to Vss DDQ DDQ V V Voltage on any pin relative ...
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Registered DIMM 13.0 AC & DC Input Measurement Levels 13.1 AC and DC Logic Input Levels for Single-ended Signals Single Ended AC and DC input levels for Command and Address Symbol Parameter V (DC) DC input logic high IH.CA V ...
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Registered DIMM 13.2 V Tolerances. REF The dc-tolerance limits and ac-noise limits for the reference voltages function of time. (V stands for V REF REF V (DC) is the linear average of V (t) over ...
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Registered DIMM 13.3 AC and DC Logic Input Levels for Differential Signals 13.3.1 Differential Signals Definition V .DIFF.AC.MIN .DIFF.AC.MAX IL Figure 3 : Definition of differential ac-swing and "time above ac level" tDVAC 13.3.2 ...
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Registered DIMM 13.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately ...
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Registered DIMM 13.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) ...
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Registered DIMM 14.0 AC and DC Output Measurement Levels 14.1 Single Ended AC and DC Output Levels Single Ended AC and DC output levels Symbol Parameter V (DC) DC output high measurement level (for IV curve linearity (DC) ...
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Registered DIMM 14.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V V (AC) for differential signals as shown in below. OHdiff Differential Output ...
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Registered DIMM 15.0 IDD specification definition Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8 IDD0 Inputs: partially toggling according to Table 32 ; Data IO: MID-LEVEL; ...
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Registered DIMM Symbol Description Self-Refresh Current: Extended Temperature Range (optional) TCASE 95°C; Auto Self-Refresh (ASR): Disabled IDD6ET a) LOW; CL: see Table AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at ...
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... M393B5273BH1 : 4GB (512Mx72) Module Symbol (DDR3-800@CL=6) IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P(fast exit) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 M393B5270BH1 : 4GB (512Mx72) Module Symbol (DDR3-800@CL=6) IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P(fast exit) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 ...
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... Registered DIMM M393B1K70BH1 : 8GB (1Gx72) Module Symbol (DDR3-800@CL=6) IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P(fast exit) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 M393B1K73BH1 : 8GB (1Gx72) Module Symbol (DDR3-800@CL=6) IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P(fast exit) IDD3N ...
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... Registered DIMM M393B2K70BM1 : 16GB (2Gx72) Module Symbol (DDR3-800@CL=6) IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P(fast exit) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 cF7 (DDR3-1066@CL=7) 4356 4626 2160 3096 3816 3600 3456 4896 4968 5076 6516 2160 6786 DDR3 SDRAM ...
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Registered DIMM 16.0 Input/Output Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) Input capacitance (All other input-only pins) Input/output capacitance of ZQ pin Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input ...
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Registered DIMM 17.0 Electrical Characteristics and AC timing (0 °C<T ≤95 ° 1.5V ± 0.075V; V CASE DDQ 17.1 Refresh Parameters by Device Density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval Note : ...
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Registered DIMM 17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to ...
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Registered DIMM DDR3-1333 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = 5 ...
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Registered DIMM 18.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333 Timing Parameters by Speed Bin Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock ...
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Registered DIMM Timing Parameters by Speed Bin (Cont.) Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register ...
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Registered DIMM Timing Parameters by Speed Bin (Cont.) Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid com- mand;Exit Percharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power ...
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Registered DIMM 18.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; ...
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Registered DIMM 18.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent ...
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... Registered DIMM 19.0 Physical Dimensions : 19.1 256Mbx8 based 512Mx72 Module(2 Ranks) 10.9 9.76 18.92 (2) 2.50 5.00 2.50 1.50±0.10 Detail A 19.1.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs D9 D10 D11 D12 The used device is 256M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846B-HC** 133.35 131.35 128.95 32.40 18.93 9.74 0.80 ± 0.05 3.80 0.2 ± 0.15 1 ...
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... Registered DIMM 19.2 512Mbx4 based 512Mx72 Module(1 Ranks) 9.76 10.9 18.92 (2) 2.50 5.00 2.50 1.50±0.10 Detail A 19.2.1 x72 DIMM, populated as one physical ranks of x4 DDR3 SDRAMs D9 D10 D11 D12 The used device is 512M x4 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0446B-HC** 133.35 131.35 128.95 32.40 18.93 9.74 0.80 ± 0.05 3.80 0.2 ± 0.15 1.00 Detail B D17 ...
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... Registered DIMM 19.3 512Mbx4 based 1Gx72 Module(2 Ranks) 9.76 10.9 18.92 (2) 2.50 5.00 2.50 1.50±0.10 Detail A 19.3.1 x72 DIMM, populated as one physical ranks of x4 DDR3 SDRAMs D18 D28 D29 D30 D27 D19 D20 D21 D10 D11 D12 The used device is 512M x4 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0446B-HC** 133 ...
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Registered DIMM 19.3.2 Heat Spreader Design Guide 1. FRONT PART Outside 9.26 11.9 Inside Green Line : TIM Attatch Line 80.78 2. BACK PART Outside Inside Green Line : TIM Attatch Line 133.15 ± 0.2 130.45 ± 0.15 29.77 31.4 ...
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Registered DIMM 3. CLIP PART 39.3 ± 0.2 29.77 4. DDR3 RDIMM ASS’Y View Reference thickness total (Maximum) : 7.55 (With Clip thickness) Upper Bending Tilting Gap 0.1 ~ 0.3 0.5 132.95 133.45 ± DDR3 SDRAM 39.3 ...
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... Registered DIMM 19.4 256Mbx8 based 1Gx72 Module(4 Ranks) 9.76 10.9 18.92 (2) 2.50 5.00 2.50 1.50±0.10 Detail A 19.4.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs D18 D19 D20 D21 D10 D11 D12 D27 D28 D29 D30 The used device is 256M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846B-HC** 133 ...
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... Registered DIMM 19.5 16GB based 2Gx72 Module(4 Ranks) 9.76 10.9 18.92 (2) 2.50 5.00 2.50 1.50±0.10 Detail A 19.6.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs D68/ D64/ D70/ D66/ D69 D65 D71 D67 D50/ D46/ D52/ D48/ D51 D47 D53 D49 D0/ D4/ D2/ D6 D18/ D22/ D20/ ...
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Registered DIMM 19.6.2 Heat Spreader Design Guide 1. FRONT PART Outside 9.26 11.9 Inside Green Line : TIM Attatch Line 80.78 2. BACK PART Outside Inside Green Line : TIM Attatch Line 133.15 ± 0.2 130.45 ± 0.15 29.77 31.4 ...
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Registered DIMM 3. CLIP PART 39.3 ± 0.2 29.77 4. DDR3 RDIMM ASS’Y View Reference thickness total (nominal) : 7.71 (With Clip thickness) Upper Bending Tilting Gap 0.1 ~ 0.3 0.5 132.95 133.45 ± DDR3 SDRAM 39.3 ...