m393b1k70bh1 Samsung Semiconductor, Inc., m393b1k70bh1 Datasheet - Page 2

• Manufacturer Part Number: m393b1k70bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Table Contents
1.0 DDR3 Registered DIMM Ordering Information ......................................................................................................... 5
2.0 Key Features ............................................................................................................................................................... 5
3.0 Address Configuration ............................................................................................................................................... 5
4.0 Registered DIMM Pin Configurations (Front side/Back side) ................................................................................. 6
5.0 Pin Description............................................................................................................................................................ 7
6.0 ON DIMM Thermal Sensor .......................................................................................................................................... 7
7.0 Input/Output Functional Description ........................................................................................................................ 8
8.0 Pinout comparison Based on Module Type ............................................................................................................. 9
9.0 Registering Clock Driver Specification................................................................................................................... 10
10.0 Functional Block Diagram: .................................................................................................................................... 11
11.0 Absolute Maximum Ratings ................................................................................................................................... 21
12.0 AC & DC Operating Conditions ............................................................................................................................. 21
13.0 AC & DC Input Measurement Levels ..................................................................................................................... 22
14.0 AC and DC Output Measurement Levels .............................................................................................................. 27
Registered DIMM
9.1 Timing & Capacitance values ............................................................................................................................ 10
9.2 Clock driver Characteristics .............................................................................................................................. 10
10.1 4GB, 512Mx72 Module(Populated as 2 rank of x8 DDR3 SDRAMs) ............................................................. 11
10.2 4GB, 512Mx72 Module(Populated as 1 ranks of x4 DDR3 SDRAMs) ........................................................... 12
10.3 8GB, 1Gx72 Module(Populated as 2 ranks of x4 DDR3 SDRAMs)................................................................ 13
10.4 8GB, 1Gx72 Module(Populated as 4 ranks of x8 DDR3 SDRAMs)................................................................ 15
10.5 16GB,2Gx72 Module(Populated as 4 ranks of x4 DDR3 SDRAMs)............................................................... 16
11.1 Absolute Maximum DC Ratings....................................................................................................................... 21
11.2 DRAM Component Operating Temperature Range........................................................................................ 21
12.1 Recommended DC Operating Conditions (SSTL - 15)................................................................................... 21
13.1 AC and DC Logic Input Levels for Single-ended Signals.............................................................................. 22
13.2 VREF Tolerances. ............................................................................................................................................. 23
13.3 AC and DC Logic Input Levels for Differential Signals ................................................................................. 24
13.4 Slew Rate Definition for Single Ended Input Signals .................................................................................... 26
13.5 Slew rate definition for Differential Input Signals .......................................................................................... 26
14.1 Single Ended AC and DC Output Levels ........................................................................................................ 27
14.2 Differential AC and DC Output Levels ............................................................................................................ 27
14.3 Single Ended Output Slew Rate ...................................................................................................................... 27
14.4 Differential Output Slew Rate .......................................................................................................................... 28
13.3.1 Differential Signals Definition ................................................................................................................. 24
13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) .................................. 24
13.3.3 Single-ended Requirements for Differential Signals ............................................................................ 25
13.3.4 Differential Input Cross Point Voltage ................................................................................................... 26
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Rev. 1.0 December 2008
DDR3 SDRAM