m393b1k70bh1 Samsung Semiconductor, Inc., m393b1k70bh1 Datasheet - Page 8

• Manufacturer Part Number: m393b1k70bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

7.0 Input/Output Functional Description
Registered DIMM
RAS, CAS, WE
TDQS[17:9],
TDQS[17:9]
DQS[17:0]
DQS[17:0]
10/AP,9:0]
12/BC,11,
DQ[63:0],
Symbol
CKE[1:0]
ODT[1:0]
A[15:13,
V
V
DM[8:0]
V
Err_Out
BA[2:0]
CB[7:0]
SA[2:0]
EVENT
RESET
Par_In
S[3:0]
TEST
REFDQ
REFCA
SDA
DDSPD
CK0
CK0
SCL
Supply
Supply
Supply
Type
(open
drain)
(open
drain)
Input
Input
Input
Input
Input
Input
Input
Input
OUT
OUT
OUT
I/O
I/O
I/O
I/O
IN
IN
IN
IN
Active High
Active High On-Die Termination control signals
Active Low
Active Low
Active Low
Polarity
Negative
Positive
Edge
Edge
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers
and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored and previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both
inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in
the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg-
ister outputs.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be exe-
cuted by the SDRAM.
Reference voltage for DQ0-DQ63 and CB0-CB7
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank
address also determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/
Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur-
ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8
identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during
Mode Register Set commands.
Data and Check Bit Input/Output pins
Active High Masks write data when high, issued concurrently with input data.
V
V
Positive Edge Positive line of the differential data strobe for input and output data.
Negative Edge Negative line of the differential data strobe for input and output data.
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will
enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When dis-
abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.
X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either V
address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V
This signal indicates that a thermal event has been detected in the thermal sensing device.The system
should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.
Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from
3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When
low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set
to low level (the Clock Driver will remain synchronized with the input clock)
Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)
Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out
bus line to V
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
DD
TT
, V
Supply Termination Voltage for Address/Command/Control/Clock nets.
SS
Supply Power and ground for the DDR SDRAM input buffers and core logic.
DD
on the system planar to act as a pull up.
DDSPD
8 of 51
on the system planar to act as a pullup.
DDSPD
on the system planar to act as a pullup.
Function
SS
or V
DDSPD
to configure the serial SPD EEPROM
Rev. 1.0 December 2008
DDR3 SDRAM