m393b5173dz1 Samsung Semiconductor, Inc., m393b5173dz1 Datasheet - Page 10

• Manufacturer Part Number: m393b5173dz1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

9.0 Registering Clock Driver Specification
9.1 Timing & Capacitance values
9.2 Clock driver Characteristics
Registered DIMM
C
C
IN
C
Symbol
Symbol
t
IN
t
t
jit
IN
t
fclock
CH
(CLOCK)
jit
t
jit
t
t
t
t
t
t
t
(hper)
dynoff
STAB
CKsk
t
(DATA)
Qsk1
Qsk1
PDM
ACT
t
t
fdyn
(per)
(RST)
DIS
SU
t
EN
(cc)
H
/t
CL
Cycle-to-cycle period jitter
Stabilization time
Dynamic phase offset
Clcok Output skew
Yn Clock Period jitter
Half period jitter
Qn Output to clock tolerance (Standard 1/2 -Clcok
Pre-Launch)
Output clock tolerance (3/4 Clock Pre-Launch)
Maximum re-driven dynamic clock off-set
Input Clock Frequency
Pulse duration, CK, CK HIGH or LOW
Inputs active time4 before RESET is taken HIGH
Setup time
Hold time
Propagation delay, single-bit switching
output disable time(1/2-Clock pre-launch)
output disable time(3/4-Clock pre-launch)
output enable time(1/2-Clock pre-launch)
output enable time(3/4-Clock pre-launch)
Data Input Capacitance
Data Input Capacitance
Reset Input Capacitance
Parameter
Parameter
10 of 64
application frequency
DCKE0/1 = LOW and
DCS0/1 = HIGH
Input valid before CK/CK
Input to remain Valid after CK/
CK
CK/CK to output
CK/CK to output float
CK/CK to output driving
Output Inversion enabled
OUtput Inversion disabled
Output Inversion enabled
OUtput Inversion disabled
Conditions
Conditions
V
V
Min
0.65
0.25
Min
-100
-100
-100
-100
DD
300
100
175
DD
-50
-40
-50
-80
0.4
0.5
1.5
8
2
0
-
-
-
-
Rev. 1.1 August 2008
T
= 1.5 ± 0.075V
= 1.5 ± 0.075V
T
C
C
= TBD
= TBD
DDR3 SDRAM
Max
Max
0.25
670
200
300
200
300
1.0
0.5
2.5
40
50
50
40
50
80
3
3
6
-
-
-
-
-
-
Units Notes
Units Notes
MHz
t
t
t
t
pF
ps
us
ps
ps
ps
ps
ps
ps
ps
ps
ns
CK
CK
CK
CK