m393b5173dz1 Samsung Semiconductor, Inc., m393b5173dz1 Datasheet - Page 15

• Manufacturer Part Number: m393b5173dz1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

EVENT
Notes :
1. DQ-to-I/O wiring may be changed within a nibble.
2. See wiring diagrams for resistor values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240 +/-1%)ohms...
Registered DIMM
SCL
SCL
DQ[35:32]
DQ[63:60]
DQ[59:56]
CB[47:44]
Serial PD w/ stand alone Thermal sensor
DQS14
DQS14
DQS16
DQS16
DQS10
DQS10
DQS4
DQS4
VSS
VSS
VSS
VSS
Vtt
WP
EVENT
Thermal sensor
Serial PD
SA0 SA1 SA2
SA0 SA1 SA2
A0
A0
Option 1
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
A1
A1
A2
A2
D14
D4
D16
D7
SDA
SDA
EVENT
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
V
V
V
V
V
V
SCL
DDSPD
DD
TT
REFCA
REFDQ
SS
Serial PD w/ integrated Thermal sensor
Integrated Thermal sensor in SPD
D32
D22
D34
D25
EVENT
Option 2
SA0 SA1 SA2
A0
A1
A2
15 of 64
DQ[43:40]
DQ[55:52]
DQ[51:48]
CB[39:36]
DQS13
DQS13
DQS15
DQS15
Serial PD
D0 - D35
D0 - D35
D0 - D35
D0 - D35
DQS5
DQS5
DQS6
DQS6
VSS
VSS
VSS
VSS
SDA
Vtt
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
SCL
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
Serial PD, no Thermal sensor
D13
D5
D15
D6
RESET
S0
S1
CK0
CK0
CK0
CK0
WP
PAR_IN
Serial PD
120Ω
Option 3
SA0 SA1 SA2
±3%
A0
RST
1:2
R
E
G
S
E
R
T
A1
I
RST : SDRAMs D[35:0]
A2
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4], D[16:13]
PCK1A -> CK: SDRAMs D[21:18], D[30:26], D35
PCK1B -> CK: SDRAMs D[25:22], D[34:31]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4], D[16:13]
PCK1A -> CK: SDRAMs D[21:18], D[30:26], D35
PCK1B -> CK: SDRAMs D[25:22], D[34:31]
ERR_OUT
Rev. 1.1 August 2008
RS0A -> CS0 : SDRAMs D[3:0], D[12:0], D17
RS0B -> CS0 : SDRAMs D[7:4], D[16:13]
RS1A -> CS1 : SDRAMs D[21:18], D[30:26], D35
RS1B -> CS1 : SDRAMs D[25:22], D[34:31]
RBA[N:0]A -> BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[N:0]B -> BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RA[N:0]A -> A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RA[N:0]B -> A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RRASA -> RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA -> CAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
RCASB -> CAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
RWEA -> WE: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
RWEB -> WE: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
RCKE0A -> CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B -> CKE0: SDRAMs D[7:4], D[16:13]
RCKE1A -> CKE1: SDRAMs D[21:18], D[30:26], D35
RCKE1B -> CKE1: SDRAMs D[25:22], D[34:31]
RODT0A -> ODT0: SDRAMs D[3:0], D[12:8], D17
RODT0B -> ODT0: SDRAMs D[7:4], D[16:13]
RODT1A -> ODT1: SDRAMs D[21:18], D[30:26], D35
RODT1B -> ODT1: SDRAMs D[25:22], D[34:31]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
DQS
DQS
DM
DQ[3:0]
SDA
DDR3 SDRAM
D31
D23
D33
D24