m393b5173dz1 Samsung Semiconductor, Inc., m393b5173dz1 Datasheet - Page 38

• Manufacturer Part Number: m393b5173dz1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

DDR3-1333 Speed Bins
17.3.1 Speed Bin Table Notes
Absolute Specification (T
Note :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin
4. "Reserved" settings are not allowed. User must program a different value.
5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production
Intermal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
Supported CL Settings
Supported CWL Settings
Registered DIMM
to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns)
when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL".
(i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
sheet and/or the DIMM SPD information if and how this setting is supported.
Tests but verified by Design/Characterization.
Tests but verified by Design/Characterization.
Tests but verified by Design/Characterization.
Parameter
OPER
CL-nRCD-nRP
; V
Speed
DDQ
CWL = 5,6
CWL = 5,6
= V
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 7
CWL = 7
DD
= 1.5V +/- 0.075 V);
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Symbol
tRCD
tRAS
tRP
tRC
tAA
38 of 64
1.875
1.875
13.5
13.5
13.5
49.5
min
2.5
1.5
1.5
36
DDR3-1333
(Optional)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
9 -9 - 9
6,7,8,9
5,6,7
9*tREFI
<1.875
<1.875
max
<2.5
<2.5
3.3
20
-
-
-
Rev. 1.1 August 2008
DDR3 SDRAM
Units
nCK
nCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3,4,7
1,2,3,4,7
1,2,3,4,
1,2,3,4,
1,2,3,7
1,2,3,7
1,2,3,4
Note
1,2,3
8
4
4
4
4
4
5