m393b5173dz1 Samsung Semiconductor, Inc., m393b5173dz1 Datasheet - Page 31

• Manufacturer Part Number: m393b5173dz1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
g) IDD current measure method and detail patterns are described on DDR3 component datasheet
Registered DIMM
IDD6ET
IDD6TC
IDD7
Symbol
Description
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Extendede); CKE: Low; External clock: Off; CK and CK:
LOW; CL: AC Timing Table ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Extended Temper-
ature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
Auto Self-Refresh Current (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK:
LOW; CL: AC Timing Table ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0; Bank Activity: Auto
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: AC Timing Table; BL: 8a); AL: CL-1; CS: High between ACT and RDA; Com-
mand, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0;
Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Reg-
istersb); ODT Signal: stable at 0
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Rev. 1.1 August 2008
DDR3 SDRAM