m393b5173dz1 Samsung Semiconductor, Inc., m393b5173dz1 Datasheet - Page 46

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m393b5173dz1

Manufacturer Part Number
m393b5173dz1
Description
Ddr3 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
Figure 9 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
Registered DIMM
Note :Clock and Strobe are drawn on a different time scale.
(for ADD/CMD with respect to clock).
V
V
V
Setup Slew Rate
V
V
V
IL
IL
Falling Signal
REF
DDQ
IH
IH
(DC) max
(AC) max
(DC) min
(AC) min
(DC)
DQS
DQS
CK
CK
V
SS
V
region
REF
=
Delta TF
to ac
V
REF
(DC) - V
Delta TF
nominal slew
tDS
tIS
IL
rate
tVAC
(AC)max
tDH
46 of 64
tIH
Setup Slew Rate
Rising Signal
Delta TR
nominal
slew rate
tDS
tIS
tVAC
=
V
IH
(AC)min - V
tDH
tIH
V
Delta TR
REF
region
to ac
Rev. 1.1 August 2008
REF
(DC)
DDR3 SDRAM

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