m393b5173dz1 Samsung Semiconductor, Inc., m393b5173dz1 Datasheet - Page 2

• Manufacturer Part Number: m393b5173dz1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Table Contents
1.0 DDR3 Registered DIMM Ordering Information .......................................................................................................... 5
2.0 Key Features ................................................................................................................................................................ 5
3.0 Address Configuration ................................................................................................................................................ 5
4.0 Registered DIMM Pin Configurations (Front side/Back side) .................................................................................. 6
5.0 Pin Description ............................................................................................................................................................. 7
6.0 ON DIMM Thermal Sensor ........................................................................................................................................... 7
7.0 Input/Output Functional Description ......................................................................................................................... 8
8.0 Pinout comparison Based on Module Type .............................................................................................................. 9
14.0 AC and DC Output Measurement Levels ............................................................................................................... 28
15.0 IDD specification definition ..................................................................................................................................... 30
9.0 Registering Clock Driver Specification .................................................................................................................... 10
10.0 Functional Block Diagram: ..................................................................................................................................... 11
11.0 Absolute Maximum Ratings .................................................................................................................................... 22
12.0 AC & DC Operating Conditions .............................................................................................................................. 22
13.0 AC & DC Input Measurement Levels ...................................................................................................................... 23
16.0 Input/Output Capacitance ....................................................................................................................................... 35
Registered DIMM
9.1 Timing & Capacitance values ............................................................................................................................. 10
9.2 Clock driver Characteristics ............................................................................................................................... 10
10.1 1GB, 128Mx72 Module(Populated as 1 rank of x8 DDR3 SDRAMs) .............................................................. 11
10.2 2GB, 256Mx72 Module(Populated as 2 rank of x8 DDR3 SDRAMs) .............................................................. 12
10.3 2GB, 256Mx72 Module(Populated as 1 ranks of x4 DDR3 SDRAMs) ............................................................ 13
10.4 4GB, 512Mx72 Module(Populated as 2 ranks of x4 DDR3 SDRAMs) ............................................................ 14
10.5 4GB, 512Mx72 Module(Populated as 4 ranks of x8 DDR3 SDRAMs) ............................................................ 16
10.6 8GB,1Gx72 Module(Populated as 4 ranks of x4 DDR3 SDRAMs) .................................................................. 17
11.1 Absolute Maximum DC Ratings ........................................................................................................................ 22
11.2 DRAM Component Operating Temperature Range ......................................................................................... 22
12.1 Recommended DC Operating Conditions (SSTL - 15) .................................................................................... 22
13.1 AC and DC Logic Input Levels for Single-ended Signals ............................................................................... 23
13.2 V
13.3 AC and DC Logic Input Levels for Differential Signals .................................................................................. 25
13.4 Slew Rate Definition for Single Ended Input Signals ..................................................................................... 27
13.5 Slew rate definition for Differential Input Signals ........................................................................................... 27
14.1 Single Ended AC and DC Output Levels ......................................................................................................... 28
14.2 Differential AC and DC Output Levels ............................................................................................................. 28
14.3 Single Ended Output Slew Rate ....................................................................................................................... 28
14.4 Differential Output Slew Rate ........................................................................................................................... 29
15.1 IDD SPEC Table .................................................................................................................................................. 32
13.3.1 Differential Signals Definition ................................................................................................................. 25
13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) .................................. 25
13.3.3 Single-ended Requirements for Differential Signals ............................................................................ 26
13.3.4 Differential Input Cross Point Voltage ................................................................................................... 27
REF
Tolerances. ................................................................................................................................................ 24
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Rev. 1.1 August 2008
DDR3 SDRAM