m395t5163qz4 Samsung Semiconductor, Inc., m395t5163qz4 Datasheet - Page 12

• Manufacturer Part Number: m395t5163qz4
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

2.8 Interfaces
Figure12 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FBD links, one DDR2 channel and an SM-
Bus interface. Each FBD link connects the Advanced Memory Buffer to a host memory controller or an adjacent FBD. The DDR2 channel
supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM
The FBDIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel.
The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound
data path each DIMM receives the data and again redrives the data to the next DIMM until the last DIMM receives the data. The last DIMM
in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). On the northbound data path each DIMM
receives the data and re-drives the data to the next DIMM until the host is reached.
3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE
The Advanced Memory Buffer supports one FBD Channel consisting of two bidirectional link interfaces using high-speed differential point-
to-point electrical signaling.
The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM
in the host direction. The southbound output link forwards this same data to the next FBD.
The northbound input link is 14 lanes wide and carries read return data or status information from the next FBDIMM in the chain back
towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or
status information that is generated internally.
3.1 DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two
ranks of eight banks with 16 row/column request, 64 data signals, and eight check-bit signals. There are two copies of address and com-
mand signals to support DIMM routing and electrical requirements. Four-transfer bursts are driven on the data and check-bit lines at 800
MHz.
Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware
state machines using write/read trial and error (or equivalent implementation). Hardware aligns the read data and check-bits to a single
core clock.
The Advanced Memory Buffer provides four copies of the command clock phase references (CLK[3:0]) and write data/check-bit .
3.2 SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration registers independent of the FBD
link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100
kHz. SMBus access to the Advanced Memory Buffer may be a requirement to boot a system. This provides a mechanism to set link
strength, frequency and other parameters needed to insure robust operation given platform specific configurations. It is also required for
diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the Advanced Memory
Buffer to get its unique ID.
FBDIMM
Figure 12 : Advanced Memory Buffer Interface Block Diagram
SB FBD
In Link
NB FBD
Out Link
MEMORY INTERFACE
AMB
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SMB
NB FBD
In Link
SB FBD
Out Link
Rev. 1.3 December 2008
DDR2 SDRAM