m395t5163qz4 Samsung Semiconductor, Inc., m395t5163qz4 Datasheet - Page 23

• Manufacturer Part Number: m395t5163qz4
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

6.0 ELECTRICAL CHARACTERISTICS
Table 6 : AbsoIute Maximum Ratings
Note : 1. Stresses greater than those Iisted may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other
Table 7 : Input DC Operating Conditions
Note : 1. Applies for SMB and SPD bus signals.
Table 8 : Timing Parameters
Note : 1. Defined in FB-DIMM Architecture and Protocol Spec
FBDIMM
Voltage on any pin relative to V
Voltage on V
Voltage V
Voltage on V
Storage temperature
DDR2 SDRAM device operating temperature(Ambient)
AMB device operating temperature (Ambient)
AMB supply voltage
DDR2 SDRAM supply voltage
Termination voltage
EEPROM supply voltage
SPD Input HIGH (Iogic 1) voltage
SPD Input LOW (logic 0) voltage
RESET Input HIGH (logic 1) voltage
RESET Input LOW (logic 0) voltage
Leakage Current (RESET)
Leakage Current (link)
EI Assertion Pass-Thru Timing
EI Deassertion Pass-Thru Timing
EI Assertion Duration
FBD Cmd to DDR Clk out that latches Cmd
FBD Cmd to DDR Write
DDR Read to FBD (last DIMM)
Resample Pass-Thru time
ResynchPass-Thru time
Bit Lock Interval
Frame Lock Interval
2. DDR2 SDRAMs of FBDIMM should require this specification.
2. Applies for AMB CMOS signal RESET.
3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specification.
2. Clocks defined as core clocks = 2x SCK input
3. @DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to the DRAMs
4. @ DDR2-667 - measured from latest DQS input AMB TO start of matching data frame at northbound FB-DIMM outputs.
Average periodic refresh interval
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
DD
CC
TT
pin relative to V
pin relative to V
pin relative to V
Parameter
Parameter
Parameter
SS
SS
SS
SS
Parameter
tEI Propagatet
tEID
tEI
tBitLock
tFrameLock
tREFI
Symbol
Symbol
V
V
V
V
V
IH
IH
DDSPD
IL
IL
V
V
V
(DC)
(DC)
I
I
(DC)
(DC)
CC
DD
TT
23 of 42
L
L
MIN
100
Symbol
85 °C < T
0 °C ≤ T
0.48 x V
CASE
CASE
1.455
MIN
-90
1.7
3.0
2.1
-5
V
≤ 85°C
1.075
2.075
Symbol
≤ 95°C
Typ.
TBD
IN
T
T
8.1
5.0
DD
T
V
V
V
, V
CASE
CASE
STG
CC
DD
TT
OUT
0.50 x V
Nom
1.50
1.8
3.3
Bitlock
Max.
154
119
DD
4
MIN
-0.3
-0.3
-0.5
-0.5
-55
85
0
0
DRAM
7.8
3.9
Rev. 1.3 December 2008
0.52 x V
V
1.575
MAX
MAX
DDSPD
1.75
1.75
100
110
2.3
2.3
DDR2 SDRAM
1.9
3.6
0.8
0.5
85
95
90
5
frames
frames
Units
clks
clks
clks
ns
ns
ns
ns
ns
DD
Units
Units
µs
µs
°C
°C
°C
V
V
V
V
Units
uA
uA
V
V
V
V
V
V
V
V
Notes
1,2
2
3
4
1
1
Note
-
Notes
1,2
1,2
1
1
1
1
1
1
1
2
1
2
3