m395t5163qz4 Samsung Semiconductor, Inc., m395t5163qz4 Datasheet - Page 5

• Manufacturer Part Number: m395t5163qz4
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

2.0 FBDIMM GENERALS
Figure 1 : FB-DIMM Memory System Overview
2.1 FB-DIMM Operation Overview
FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth
and scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in
limited density build-up as channel speeds increase with memory system having the stub-bus architecture. FB-DIMM solution is
intended to eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be con-
nected serially to a given channel.
Memory system architecture perspective, FB-DIMM is fully differentiated from Registered DIMM and Unbuffered DIMM. A lot of new
technologies are integrated into this solution in order to achieve this scalable higher speed memory solution. Serial link interface with
packet data format and dedicated read/write paths are key attribute in FB-DIMM protocol. Point to Point interconnect with fully differen-
tial signaling and de-emphasis scheme are key attribute in FBD channel link. Clock recovery by using data stream is key attribute in FBD
clocking. FB-DIMM supports both clock resync and resampling mode options. CRC (Cyclic Redundancy Check) bits are transferred with
data stream for reliability at high speed data transaction. Failover mechanism supports system running with dynamic IO failure. Finally
all FB-DIMM is connected in daisy chain manner. Thus, every interconnection between AMB (advanced memory buffer) to AMB, AMB to
Host and AMB to DRAM, is point to point interconnection which allows higher data transfer bandwidth.
Figure 1 shows a lot of new technologies integrated with FBD solution.
FBDIMM
P2P Interconnect
- De-Emphasis
- LVDS
Two unidirectional links
Host
- Southbound
- Northbound
- CRC fail-over
Reliability
Clock
SB (ADDR, CMD, Wdata)
NB(Rdata)
ADDR.CMD, DATA
Protocol Packet
Clock Recovery
Rx
Tx
Clk_Ref
DQs ADDR
5 of 42
DRAM
DRAM
DRAM
DRAM
AMB
CMD
CLK
Tx
Rx
Buffer
FIFO
Rx
Tx
DQs
AMB
ADDR
CMD
CLK
Rev. 1.3 December 2008
Rx
Tx
DDR2 SDRAM
Fly-by CLK, CMD
DIMM Topology
Daisy Chain
Upto 8 AMB
Connection