m395t5163qz4 Samsung Semiconductor, Inc., m395t5163qz4 Datasheet - Page 32

• Manufacturer Part Number: m395t5163qz4
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

7.0 CHANNEL INITIALIZATION
This chapter defines the process of initializing the FBD channel. The FBD initialzation process generally follows the top to bottom se-
quence of state transitions shown in the high level AMB Initialization Flow diagram in Figure The host must sequence the AMB devices
through the Disable, (back to Disable), Training, Testing, and Polling states in order to transition the AMBs into the active channel L0
state. The value in parenthesis in each state bubble indicates the condition/activity of the links during these states.
FBDIMM
The states in the AMB Initialization Flow diagram are :
Disable - The channel is inactive and the interface signals are in a low power Electrical Idle condition.
Training - The initial bit alignment and frame alignment training is done in this state.
Testing - Each bit lane is individually tested in this state.
Polling - The channel capabilities of the individual AMB devices are communicated in this state.
Config - The channel width configuration is communicated to the AMB devices in this state.
L0 - The channel is active and frames of information are flowing between the host and the AMB devices.
Recalibrate - The channel is momentarily idled to allow TX and Rx circuits to be recalibrated.
L0s - The channel is in a low-latency power saving condition. (Optional)
Each bit lane is initialized (mosly) independently to support fault tolerance. The transitions in the figure represent the transitions of the
AMB core logic state machine and are taken when the transition event is detected on the minimum required number of southound bit
lanes. The chain of FBD links connecting the host the AMBs must each be initialized to esabish the timing for broadcasting data frames
in the southbound direction and for merging data frame in the northbound direction. The AMBs on the channel are generally initialized
as a group but because each AMB is individually addressable many altemate may altemate initialization sequences may be employed.
Figure15 : AMB Initialization Flow Diagram
Recalibrate
Tranining
Power-up
Disable
Testing
Polling
Config
(NOP2)
(TS0)
(TS1)
(TS2)
(TS3)
(EI)
(EI)
L0
Calibrate
(1’s)
L0s
(EI)
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Rev. 1.3 December 2008
DDR2 SDRAM