m395t5163qz4 Samsung Semiconductor, Inc., m395t5163qz4 Datasheet - Page 14

• Manufacturer Part Number: m395t5163qz4
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

Table 4 : DDR2 240 Pin FBDIMM Configurations (Front side/Back side)
RFU = Reserved Future Use.
* These pin positions are reserved for forwarded clocks to be used in future module implementations
** These pin positions are reserved for future architecture flexibility
1. The following signals are CRC bits and thus appear out of the normal sequence : PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN12,
4.0 PIN CONFIGUREATION
FBDIMM
Pin
PS9/PS9, SS9/SS9.
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
11
1
2
3
4
5
6
7
8
9
RESET
Front
RFU**
RFU**
VID1
PN0
PN0
PN1
PN1
PN2
PN2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
SS
DD
DD
DD
SS
CC
CC
SS
CC
CC
SS
SS
SS
SS
SS
SS
TT
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
DNU/M_Test
Back
RFU**
RFU**
VID0
SN0
SN0
SN1
SN1
SN2
SN2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
SS
DD
DD
DD
SS
CC
CC
SS
CC
CC
SS
SS
SS
SS
SS
SS
TT
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
PN13
PN13
RFU*
RFU*
PN12
PN12
PN3
PN3
PN4
PN4
PN5
PN5
PN6
PN6
PN7
PN7
PN8
PN8
PN9
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
SN13
SN13
RFU*
RFU*
SN12
SN12
SN3
SN3
SN4
SN4
SN5
SN5
SN6
SN6
SN7
SN7
SN8
SN8
SN9
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
14 of 42
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front
PN10
PN10
PN11
PN11
RFU*
RFU*
PN9
PS0
PS0
PS1
PS1
PS2
PS2
PS3
PS3
PS4
PS4
PS9
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
KEY
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back
SN10
SN10
SN11
SN11
RFU*
RFU*
SN9
SS0
SS0
SS1
SS1
SS2
SS2
SS3
SS3
SS4
SS4
SS9
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
Rev. 1.3 December 2008
Pin
100
101
102
103
104
105
106
107
108
109
117
118
120
110
111
112
113
114
115
116
119
91
92
93
94
95
96
97
98
99
DDR2 SDRAM
Front
RFU**
RFU**
SDA
PS9
PS5
PS5
PS6
PS6
PS7
PS7
PS8
PS8
V
V
V
V
V
V
V
SA2
SCL
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
DD
DD
SS
DD
DD
DD
SS
DD
DD
TT
Pin
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
211
V
Back
RFU**
RFU**
SCK
SCK
DDSPD
SS9
SS5
SS5
SS6
SS6
SS7
SS7
SS8
SS8
V
V
V
V
V
SA0
SA1
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
SS
DD
DD
TT