m395t5163qz4 Samsung Semiconductor, Inc., m395t5163qz4 Datasheet - Page 24

• Manufacturer Part Number: m395t5163qz4
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

Table 9 : Power specification parameter and test condition
FBDIMM
(for AMB spec, Not in
(for AMB spec, Not in
Idd_Active_1
Idd_Active_2
Icc_Active_1
Icc_Active_2
Idd_Training
Idd_Training
Idd_Idle_0
Idd_Idle_1
Icc_Idle_0
Icc_Idle_1
Symbol
SPD)
SPD)
Idle Current, single or last DIMM
L0 state, idle (0 BW)
Primary channel enabled, Secondary Channel Disabled
CKE high. Command and address lines stable.
DRAM clock active.
Idle Current, first DIMM
L0 state, idle (0 BW)
Primary and Secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
Active Power
L0 state.
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
Active Power, data pass through
L0 state.
50% DRAM BW to downstream DIMM, 67% read, 33% write.
Primary and Secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
Training
Primary and Secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
CKE high, Command and address lines stable.
DRAM clock active.
Idd_Active_1 Total Power
Idd_Active_2 Total Power
Idd_Training Total Power
Idd_Idle_0 Total Power
Idd_Idle_1 Total Power
Conditions
24 of 42
Rev. 1.3 December 2008
DDR2 SDRAM
Supply
@1.5V
@1.8V
@1.5V
@1.8V
@1.5V
@1.8V
@1.5V
@1.8V
@1.5V
@1.8V
Power
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
W
W
W
W