m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 104

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

1.13.4
The UTOPIA level 2 specification allows for 31 unique addresses 0-30 to be assigned to devices on the UTOPIA
bus. UTOPIA address 31 is a Null address. While both the ATM and PHY side Utopia support the null address
assigned as a valid address, many connecting devices may not support this. To alleviate this, the dual Clav/Enb
mode is available to support all 32 ports. When using Dual Clav/Enb, the UTOPIA port will respond to either Clav0/
Enb0 or Clav1/Enb1 depending on the port. For the ATM side, Clav0/Enb0 is assigned to port 0 - 15 and Clav1/
Enb1 is assigned to port 16-32. Enabling of dual Clav/Enb mode for the ATM side is set in the ATMMINTFC 0xF03
register. For the PHY side, assignment of ports to Clav/Enb is configurable in the IMA_MISC_CONFIG register
0x804.
1.14
The M2852x’s ATM Transmission Convergence (TC) block is responsible for recovering cell alignment using the
HEC octet, performing detection/correction, and descrambling the payload octets. The resulting ATM cells are then
passed to the ATM layer via the UTOPIA interface. Simultaneously, the ATM transmitter block is receiving data from
the ATM layer, optionally inserting header fields, optionally calculating the HEC, and sending the cells to the
framers. If no data is being received from the ATM layer, the cell processor generates idle cells based on the data
programmed into the associated registers.
1.14.1
The ATM cell transmitter controls the generation and formatting of 53-octet ATM cells that are sent to the Framer
(Line) Transmit Ports. This block formats an octet stream containing ATM data cells from the ATM layer device
when those cells are available. All 53 octets of the data cells may be obtained from the external data source and
formatted into the outgoing octet stream.
This block calculates the HEC octet in the outgoing cell from the header field. The calculated HEC octet can be
inserted in place of the incoming data octet by writing DisHEC (bit 7) in the CGEN register (0x08) to a logic 0. For
testing purposes, this HEC octet can be corrupted by XORing the calculated value with a specific error pattern
input set in the ERRPAT register (0x0B). This HEC error is achieved by writing ErrHEC (bit 4) in the CGEN register
(0x08) to a logic 1. The remaining 48-octet payload field of the outgoing cell is obtained from the external data
source. The payload can be scrambled.
When there is no data from the ATM layer device, the TC Block inserts idle cells automatically in the outgoing octet
stream. The 4-octet header field for these idle cells comes from the TXIDL1–4 registers (0x14–17). The HEC octet
is calculated and inserted automatically. The payload field is filled with the octet contained in the IDLPAY register
(0x0A).
In normal operation, the 4-octet header field in the outgoing cell is passed on from the ATM layer device. Header
patterns can be modified in the TXHDR1–4 registers (0x10–13) and inserted into outgoing cells in place of header
bytes received from the ATM layer. Whether the original header cells or replacement cells are sent is controlled by
bits 0–4 in the HDRFIELD (0x09) register.
1.14.1.1
In normal operation, the M2852x calculates the HEC for the four header bytes of each cell coming from the ATM
layer. It then adds the HEC coset (55 hex, by ATM standards) and inserts the result in octet 5 of the outgoing cell.
HEC calculation can be disabled by setting bit 7 of CGEN (0x08) to a 1. When HEC is disabled, the M2852x leaves
the contents of the HEC field unchanged and transmits whatever data is placed in that field by the ATM layer.
28529-DSH-001-K
NOTE:
Dual Clav/Enb Operation
Transmission Convergence Block
ATM Cell Transmitter
HEC Generation
When operating in the UTOPIA-to-UTOPIA mode, the ATM Cell processor block is disabled.
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