m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 233

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.5.19
This register contains the least significant bits of a 16 bit count of the number of ATM layer cells received over the
Receive ATM side UTOPIA bus for a particular UTOPIA address. The register is read only.
Rx UTOPIA Address 0 - 15
Rx UTOPIA Address 16–31
28529-DSH-001-K
0xC48
0x850
n=16
n=0
Bit
7-0
0x852
n=17
0xC4
n=1
A
Default
0
0x854
n=18
0xC4
n=2
C
IMA_RX_ATMn_CELL_COUNT_LSB (Receive Cell Count LSBs)
Receive Cell Count LSBs
0xC4E
0x856
n=19
n=3
0x950
n=20
Name
0xCC
n=4
8
0x952
Mindspeed Proprietary and Confidential
n=21
0xCC
Mindspeed Technologies
n=5
A
0x954
n=22
0xCC
n=6
Receive Cell Count: This field contains the least significant bits of a 16 bit count of the
number of ATM layer cells received over the specific UTOPIA address. A write operation
with data = 0x01 to the first address (0x850 for Address 0, 0x852 for Address 1, etc.)
transfers the state of all 16 bits of the counter to registers that are accessible to the
microprocessor bus and clears the counter. A read operation should then be performed to
read the previous state of the counter. The first address should be read first. The second
address (0x851 for Address 0, 0x853 for Address 1, etc.) is read next. A write operation
with data = 0x00 to the first address of each group returns back to the raw counters.
C
M28525 -- Not Applicable
0x956
n=23
0xCC
n=7
E
M28529
M28525
M28529
0xA50
n=24
0xD4
n=8
8
0xA52
n=25
0xD4
n=9
®
A
0xA54
n=26
n=10
0xD4
C
Description
0xA56
n=27
n=11
0xD4
E
0xB50
n=28
n=12
0xDC
8
0xB52
n=29
n=13
0xDC
A
0xB54
n=30
n=14
0xDC
Registers
C
0xB56
n=31
n=15
0xDC
E
218