m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 166

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.2.2
The ENSUMINT register controls which of the interrupts listed in the SUMINT register (0x00) appear in the
SUMPORT register and on the MicroInt* (pin AA1), provided the corresponding ENSUMPORT bit is enabled and
EnIntPin (bit 3) in the GENCTRL register (0xF00) is enabled.
28529-DSH-001-K
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x01—ENSUMINT (Summary Interrupt Control Register)
EnTxCellInt
EnRxCellInt
Name
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—
—
—
—
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Mindspeed Proprietary and Confidential
Mindspeed Technologies
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
When written to a logical 1, this bit enables the transmit cell interrupts located in the TxCellInt
register (0x2C). These interrupts appear can on the MicroInt* pin (pin AA1), provided that
EnPortInt in the ENSUMPORT0-3 register (0x0F06, 0x0F08, 0x0F0A, 0x0F0C) is enabled for this
port and EnIntPin (bit 3) in the GENCTRL register (0x0F00) is enabled.
When written to a logical 1, this bit enables the receive cell interrupts located in the RxCellInt
register (0x2D). These interrupts can appear on the MicroInt* pin (pin AA1), provided that
EnPortInt in the ENSUMPORT0-3 register (0x0F06, 0x0F08, 0x0F0A, 0x0F0C) is enabled for this
port and EnIntPin (bit 3) in the GENCTRL register (0x0F00) is enabled.
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Description
Registers
151