m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 62

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

Table 1-11.
28529-DSH-001-K
phyUTxData[0]
phyUTxData[1]
phyUTxData[2]
phyUTxData[3]
phyUTxData[4]
phyUTxData[5]
phyUTxData[6]
phyUTxData[7]
phyUTxData[8]
phyUTxData[9]
phyUTxData[10]
phyUTxData[11]
phyUTxData[12]
phyUTxData[13]
phyUTxData[14]
phyUTxData[15]
phyUTxEnb[0]*
phyUTxEnb[1]*
phyUTxSOC
phyUTxPrty
IMA_SysClk
IMA_RefClk
TxTRL[0]
TxTRL[1]
Pin Label
M2852x Pin Descriptions (7 of 18)
PHY UTOPIA Transmit
Data
PHY UTOPIA Transmit
Enable
PHY UTOPIA Transmit
Start of Cell
PHY UTOPIA Transmit
Parity
IMA Subsystem Clock
IMA Reference Clock
Transmit Reference
Clocks
Signal Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
AD10
AD5
AD4
No.
AF4
AE4
AC6
AF3
AF2
AC4
AE9
E18
E16
A19
B19
M1
M3
P1
N1
N3
N4
N5
L1
E1
F3
I/PU
I/PU
I/O
O
O
O
O
O
Transmit Reference Clocks.
8 bit PHY Cell Data to be sent out the PHY facility.
8 bit UTOPIA interface used to transmit data to the external TC
devices.
Data transfer enable for Transmit PHY cells (active low signal). To
support different PHY devices, separate enable signals are
provided. When the PHY Size (bits 4 and 5) of register 0x804 are
set to 2 (single clav), phyUTxEnb[1] must be pulled up.
Start of Cell synchronization signal for Transmit PHY cells (active
high). Indicates that the first byte of a cell is being placed on the
phyUTxData[7:0] bus.
Odd parity calculated over phyUTxData[15:0] pins in 16-bit mode
and over phyUTxData[7:0] pins in 8-bit mode.
Most of the IMA logic circuits use this clock (or a derivative of it). It
can also be used as a T1/E1 reference clock. Refer to
If this is to be used as a reference clock, set the frequency as
shown in
®
Section
1.12.
Description
Functional Description
Section
1.12.
47