mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 186

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

FlexRay Module (FLEXRAYV2)
3.4.11
The application of the external rate and offset correction is triggered when the application writes to the
EOC_AP and ERC_AP fields in the
external correction values in the next even-odd cycle pair as shown in
If the offset correction applied in the NIT of cycle 2n+1 shall be affect by the external offset correction,
the EOC_AP field must be written to after the start of cycle 2n and before the end of the static segment of
cycle 2n+1. If this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed
that the external correction value is applied in cycle 2n+1. If the value is not applied in cycle 2n+1, then
the value will be applied in the cycle 2n+3. Refer to
If the rate correction for the cycle pair [2n+2, 2n+3] shall be affect by the external offset correction, the
ERC_AP field must be written to after the start of cycle 2n and before the end of the static segment start
of cycle 2n+1. If this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed
that the external correction value is applied in cycle pair [2n+2, 2n+3]. If the value is not applied for cycle
pair [2n+2, 2n+3], then the value will be applied for cycle pair [2n+4, 2n+5]. Refer to
details.
3.4.12
The FlexRay protocol requires the provision of a snapshot of the Synchronization Frame ID tables for the
even and odd communication cycle for both channels. The FlexRay module provides the means to write a
copy of these internal tables into the FRM and ensures application access to consistent tables by means of
table locking. Once the application has locked the table successfully, the FlexRay module will not
overwrite these tables and the application can read a consistent snapshot.
186
static segment
External Clock Synchronization
Sync Frame ID and Sync Frame Deviation Tables
static segment
Only synchronization frames that have passed the synchronization frame
filters are considered for clock synchronization and appear in the sync frame
tables.
cycle 2n
ERC_AP write window
Figure 3-133. External Offset Correction Write and Application Timing
Figure 3-134. External Rate Correction Write and Application Timing
cycle 2n
EOC_AP write window
NIT
static segment
NIT
Protocol Operation Control Register
cycle 2n+1
MFR4300 Data Sheet, Rev. 3
static segment
NOTE
cycle 2n+1
NIT
Figure 3-133
static segment
cycle 2n+2
NIT
for timing details.
EOC_AP application
ERC_AP application
Figure 3-133
NIT
(POCR). The PE applies the
static segment
cycle 2n+3
Freescale Semiconductor
and
Figure 3-134
Figure
NIT
3-134.
for