mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 227
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mfr4300
Manufacturer Part Number
mfr4300
Description
Flexray Communication Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MFR4300.pdf
(266 pages)
- Current page: 227 of 266
- Download datasheet (2Mb)
6.4.2
The interface mode selection is done when the TXD_BG[1:2]/IF_SEL[1:0] pins are in the IF_SEL[1:0]
mode. In the TXD_BG[1:2] modes the pads are outputs from the MFR4300 device.
6.4.2.1
The interface selection is made upon the levels on the bus signal IF_SEL[1:0] while a power-on, low
voltage, clock monitor or external reset process is ongoing. The CRG latches the IF_SEL[1:0] during the
latching window as presented on
Freescale Semiconductor
clock monitor failure
Figure 6-7. Interface Selection during Power-on or Low Voltage Reset or Clock Monitor Failure
low voltage reset or
power-on reset or
IF_SEL[1:0]
Interface Selection
Interface and AMI Clock Selection
The PIM block selects the TXD_BG[1:2]/IF_SEL[1:0] pads modes based
on the system reset signal.
system reset
CRSR.ERIF
INT_CC#
RESET#
Figure 6-7
Figure 6-6. External Reset
MFR4300 Data Sheet, Rev. 3
and
~16380 EXTAL/CLK_CC periods
Figure
NOTE
~16410 EXTAL/CLK_CC periods
6-8.
~70 EXTAL/CLK_CC periods
Latching window
Clocks and Reset Generator (CRG)
227
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