mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 201

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.4.20
The Clock Domain Crossing module CDC implements the signal crossing from the CHI clock domain to
the PE clock domain and vice versa. The signal crossing logic is implemented as a three-stage pipe-line.
Two pipe-line stages are used for clock synchronization; the third stage is used for pulse generation.
3.4.20.1
Due to the clock domain crossing implementation, each signal from the PE to the CHI is delayed by at least
two CHI clock cycles and by at most three CHI clock cycles. In terms of time, the signal latency time t
for a given CHI frequency f
3.5
This section provides information for initializing and using the FlexRay module.
3.5.1
The full FlexRay module is reset with the hard reset. Additionally, the protocol engine is reset in the Stop
Mode and as a result of the RESET protocol command issued using the
Register
The hard reset resets all internal registers and all registers in the FlexRay module memory map. The
protocol engine reset resets only the registers in the protocol engine. All registers in memory are not reset.
The following is an initialization sequence applicable to the FlexRay module after a hard reset
Freescale Semiconductor
1. Configure FlexRay module
2. Enable the FlexRay module
3. Configure the Protocol Engine
4. Configure the Message Buffers and FIFOs
— set the control bits in the
— set the MEN bit in the
— the FlexRay module enters the Normal Mode
— write the CONFIG command into the POCCMD field of the
— write to the PCR[0:31] registers to set all protocol parameters.
— set the number of message buffers used and the message buffer segmentation in the
— define the message buffer data size in the
— configure each message buffer by setting the configuration values in the
(POCR).
Initialization Information
Register (POCR)
Buffer Segment Size and Utilization Register (MBSSUTR)
Configuration, Control, Status Registers
Registers
Index Registers (MBIDXRn)
Clock Domain Crossing
FlexRay Initialization Sequence
Clock Domain Crossing Signal Latency
(MBCCFRn),
chi
is
Module Configuration Register (MCR)
Message Buffer Frame ID Registers
Module Configuration Register (MCR)
MFR4300 Data Sheet, Rev. 3
------- -
f
2
chi
d
t
lat
d
------- -
f
chi
(MBCCSRn),
3
Message Buffer Data Size Register (MBDSR)
Message Buffer Cycle Counter Filter
Protocol Operation Control
Protocol Operation Control
(MBFIDRn),
FlexRay Module (FLEXRAYV2)
Message Buffer
Message Buffer
Message
Eqn. 3-26
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lat