IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 20

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
Q
NOTES:
1. Retransmit setup is complete after
2.
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
5.
WCLK
RCLK
0
Retransmit setup procedure. D = 8,192 for IDT72255LA and 16,384 for IDT72265LA.
EF
OE
- Q
1
goes HIGH at 60 ns + 1 RCLK cycle + t
= first word written to the FIFO after Master Reset, W
= LOW.
n
t
ENS
W
x
t
A
t
ENH
t
ENS
EF
t
RTS
returns HIGH, only then can a read operation begin.
t
RTS
REF
Figure 11. Retransmit Timing (IDT Standard Mode)
.
t
t
t
2
ENH
REF
HF
t
SKEW2
= second word written to the FIFO after Master Reset.
1
W
x+1
2
t
PAF
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
t
ENS
2
t
t
t
A
REF
PAE
(5)
FF
W
will be HIGH throughout the
1
(3)
4670 drw 14
t
t
A
ENH
W
2
20
(3)