IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 24

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
gether the control signals of multiple devices. Status flags can
be detected from any one device. The exceptions are the
and
functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for
and
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
DEPTH EXPANSION CONFIGURATION (FWFT MODE
ONLY)
requiring depths greater than 8,192 and 16,384 for the
IDT72265LA with an 18-bit bus width. In FWFT mode, the
FIFOs can be connected in series (the data outputs of one
FIFO connected to the data inputs of the next) with no external
logic necessary. The resulting configuration provides a total
depth equivalent to the sum of the depths associated with
each single FIFO. Figure 24 shows a depth expansion using
two IDT72255LA/72265LA devices.
Reset for all FIFOs in the depth expansion configuration. The
first word written to an empty configuration will pass from one
FIFO to the next ("ripple down") until it finally appears at the
The IDT72255LA can easily be adapted to applications
Care should be taken to select FWFT mode during Master
Word width may be increased simply by connecting to-
IR
FF
GATE
/
OR
functions in IDT Standard mode and the
(1)
FIRST WORD FALL THROUGH/
DATA IN
assertion to vary by one cycle between FIFOs. In
SERIAL INPUT (FWFT/SI)
MASTER RESET (
PARTIAL RESET (
FULL FLAG/INPUT READY (
FULL FLAG/INPUT READY (
RETRANSMIT (
m + n
PROGRAMMABLE (
WRITE CLOCK (WCLK)
WRITE ENABLE (
HALF-FULL FLAG (
Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion
)
)
)
D
0
- Dm
LOAD (
/ )
/ ) #2
m
#1
EF
)
)
)
)
/
FF
72255LA
72265LA
FIFO
deassertion
IDT
#1
IR
and
Dm
m
OR
+1
EF
- Dn
Q
0
n
- Qm
IDT Standard mode, such problems can be avoided by
creating composite flags, that is, ANDing
and separately ANDing
composite flags can be created by ORing
and separately ORing
IDT72255LA/72265LA devices. D
form a 36-bit wide input bus and Q
a 36-bit wide output bus. Any word width can be attained by
adding additional IDT72255LA/72265LA devices.
outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO,
that device's
FIFO in line.
it takes for
data to appear on the last FIFO's outputs) after a word has
been written to the first FIFO is the sum of the delays for each
individual FIFO:
where N is the number of FIFOs in the expansion and T
is the RCLK period. Note that extra cycles should be added
for the possibility that the t
For an empty expansion configuration, the amount of time
Figure 23 demonstrates a width expansion using two
72255LA
72265LA
FIFO
IDT
#2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
OR
OR
READ CLOCK (RCLK)
n
(N – 1)*(4*transfer clock) + 3*T
READ ENABLE (
OUTPUT ENABLE (
EMPTY FLAG/OUTPUT READY (
EMPTY FLAG/OUTPUT READY (
PROGRAMMABLE (
of the last FIFO in the chain to go LOW (i.e. valid
Qm
line goes LOW, enabling a write to the next
+1
- Qn
IR
FF
of every FIFO.
of every FIFO. In FWFT mode,
SKEW3
)
)
m + n
)
0
-Q
0
specification is not met
17
- D
from each device form
DATA OUT
17
/
/
OR
EF
from each device
) #2
) #1
RCLK
of every FIFO,
4670 drw 22
of every FIFO,
GATE
(1)
24
RCLK